u-boot/arch/xtensa/cpu/exceptions.c
Chris Zankel c978b52410 xtensa: add support for the xtensa processor architecture [2/2]
The Xtensa processor architecture is a configurable, extensible,
and synthesizable 32-bit RISC processor core provided by Tensilica, inc.

This is the second part of the basic architecture port, adding the
'arch/xtensa' directory and a readme file.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-08-15 18:46:38 -04:00

44 lines
854 B
C

/*
* (C) Copyright 2008 - 2013 Tensilica Inc.
* (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Exception handling.
* We currently don't handle any exception and force a reset.
* (Note that alloca is a special case and handled in start.S)
*/
#include <common.h>
#include <command.h>
#include <asm/string.h>
#include <asm/regs.h>
typedef void (*handler_t)(struct pt_regs *);
void unhandled_exception(struct pt_regs *regs)
{
printf("Unhandled Exception: EXCCAUSE = %ld, EXCVADDR = %lx, pc = %lx\n",
regs->exccause, regs->excvaddr, regs->pc);
panic("*** PANIC\n");
}
handler_t exc_table[EXCCAUSE_LAST] = {
[0 ... EXCCAUSE_LAST-1] = unhandled_exception,
};
int interrupt_init(void)
{
return 0;
}
void enable_interrupts(void)
{
}
int disable_interrupts(void)
{
return 0;
}