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https://github.com/AsahiLinux/u-boot
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fe63d3cfb7
Synchronize stm32f7 device tree with kernel v4.20. All pinctrl bindings are updated. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
289 lines
7.7 KiB
Text
289 lines
7.7 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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#include <dt-bindings/mfd/stm32f7-rcc.h>
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/ {
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soc {
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pinctrl: pin-controller {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x40020000 0x3000>;
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interrupt-parent = <&exti>;
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st,syscfg = <&syscfg 0x8>;
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pins-are-numbered;
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gpioa: gpio@40020000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x0 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
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st,bank-name = "GPIOA";
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};
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gpiob: gpio@40020400 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x400 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
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st,bank-name = "GPIOB";
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};
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gpioc: gpio@40020800 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x800 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
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st,bank-name = "GPIOC";
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};
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gpiod: gpio@40020c00 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0xc00 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
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st,bank-name = "GPIOD";
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};
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gpioe: gpio@40021000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1000 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
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st,bank-name = "GPIOE";
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};
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gpiof: gpio@40021400 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1400 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
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st,bank-name = "GPIOF";
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};
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gpiog: gpio@40021800 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1800 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
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st,bank-name = "GPIOG";
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};
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gpioh: gpio@40021c00 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1c00 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
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st,bank-name = "GPIOH";
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};
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gpioi: gpio@40022000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2000 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
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st,bank-name = "GPIOI";
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};
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gpioj: gpio@40022400 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2400 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
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st,bank-name = "GPIOJ";
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};
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gpiok: gpio@40022800 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2800 0x400>;
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clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
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st,bank-name = "GPIOK";
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};
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cec_pins_a: cec@0 {
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pins {
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pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
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slew-rate = <0>;
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drive-open-drain;
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bias-disable;
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};
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};
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usart1_pins_a: usart1@0 {
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pins1 {
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pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
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bias-disable;
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};
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};
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usart1_pins_b: usart1@1 {
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pins1 {
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pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
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bias-disable;
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};
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};
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i2c1_pins_b: i2c1@0 {
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pins {
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pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
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<STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
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bias-disable;
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drive-open-drain;
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slew-rate = <0>;
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};
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};
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usbotg_hs_pins_a: usbotg-hs@0 {
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pins {
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pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
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<STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
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<STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
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<STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
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<STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
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<STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
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<STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
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<STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
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<STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
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<STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
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<STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
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<STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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usbotg_hs_pins_b: usbotg-hs@1 {
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pins {
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pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
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<STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
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<STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
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<STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
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<STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
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<STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
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<STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
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<STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
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<STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
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<STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
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<STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
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<STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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usbotg_fs_pins_a: usbotg-fs@0 {
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pins {
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pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
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<STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
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<STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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sdio_pins_a: sdio_pins_a@0 {
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pins {
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pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
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<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
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<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
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<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
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<STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
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<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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sdio_pins_od_a: sdio_pins_od_a@0 {
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pins1 {
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pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
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<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
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<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
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<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
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<STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
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drive-push-pull;
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slew-rate = <2>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
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drive-open-drain;
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slew-rate = <2>;
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};
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};
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sdio_pins_b: sdio_pins_b@0 {
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pins {
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pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
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<STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
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<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
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<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
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<STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
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<STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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sdio_pins_od_b: sdio_pins_od_b@0 {
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pins1 {
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pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
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<STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
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<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
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<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
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<STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
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drive-push-pull;
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slew-rate = <2>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
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drive-open-drain;
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slew-rate = <2>;
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};
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};
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};
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};
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};
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