mirror of
https://github.com/AsahiLinux/u-boot
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5ecf9b0b8a
Add board support for StarFive VisionFive v2. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
87 lines
1.6 KiB
C
87 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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* Author: Yanhong Wang<yanhong.wang@starfivetech.com>
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*/
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#include <common.h>
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#include <asm/arch/regs.h>
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#include <asm/arch/spl.h>
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#include <asm/io.h>
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#include <log.h>
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#include <spl.h>
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#define JH7110_CLK_CPU_ROOT_OFFSET 0x0U
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#define JH7110_CLK_CPU_ROOT_SHIFT 24
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#define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24)
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int spl_board_init_f(void)
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{
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int ret;
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ret = spl_soc_init();
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if (ret) {
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debug("JH7110 SPL init failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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u32 spl_boot_device(void)
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{
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u32 mode;
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mode = in_le32(JH7110_BOOT_MODE_SELECT_REG)
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& JH7110_BOOT_MODE_SELECT_MASK;
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switch (mode) {
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case 0:
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return BOOT_DEVICE_SPI;
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case 1:
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return BOOT_DEVICE_MMC2;
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case 2:
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return BOOT_DEVICE_MMC1;
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case 3:
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return BOOT_DEVICE_UART;
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default:
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debug("Unsupported boot device 0x%x.\n", mode);
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return BOOT_DEVICE_NONE;
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}
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}
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void board_init_f(ulong dummy)
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{
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int ret;
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ret = spl_early_init();
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if (ret)
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panic("spl_early_init() failed: %d\n", ret);
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riscv_cpu_setup(NULL, NULL);
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preloader_console_init();
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/* Set the parent clock of cpu_root clock to pll0,
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* it must be initialized here
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*/
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clrsetbits_le32(JH7110_SYS_CRG + JH7110_CLK_CPU_ROOT_OFFSET,
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JH7110_CLK_CPU_ROOT_MASK,
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BIT(JH7110_CLK_CPU_ROOT_SHIFT));
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ret = spl_board_init_f();
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if (ret) {
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debug("spl_board_init_f init failed: %d\n", ret);
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return;
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}
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}
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#if CONFIG_IS_ENABLED(SPL_LOAD_FIT)
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int board_fit_config_name_match(const char *name)
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{
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/* boot using first FIT config */
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return 0;
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}
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#endif
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