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The clock access functions exported by the clk header use the struct clk_ti_reg parameter to get the address of the register. This must also apply to clk_ti_latch(). Changes to TI's clk-mux and clk-divider drivers prevented the patch from generating compile errors. Signed-off-by: Dario Binacchi <dariobin@libero.it>
253 lines
5.5 KiB
C
253 lines
5.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* TI multiplexer clock support
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*
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* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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*
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* Based on Linux kernel drivers/clk/ti/mux.c
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <clk-uclass.h>
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#include <asm/io.h>
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#include <linux/clk-provider.h>
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#include "clk.h"
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struct clk_ti_mux_priv {
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struct clk_bulk parents;
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struct clk_ti_reg reg;
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u32 flags;
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u32 mux_flags;
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u32 mask;
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u32 shift;
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s32 latch;
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};
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static struct clk *clk_ti_mux_get_parent_by_index(struct clk_bulk *parents,
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int index)
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{
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if (index < 0 || !parents)
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return ERR_PTR(-EINVAL);
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if (index >= parents->count)
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return ERR_PTR(-ENODEV);
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return &parents->clks[index];
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}
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static int clk_ti_mux_get_parent_index(struct clk_bulk *parents,
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struct clk *parent)
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{
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int i;
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if (!parents || !parent)
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return -EINVAL;
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for (i = 0; i < parents->count; i++) {
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if (parents->clks[i].dev == parent->dev)
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return i;
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}
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return -ENODEV;
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}
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static int clk_ti_mux_get_index(struct clk *clk)
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{
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struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
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u32 val;
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val = clk_ti_readl(&priv->reg);
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val >>= priv->shift;
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val &= priv->mask;
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if (val && (priv->flags & CLK_MUX_INDEX_BIT))
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val = ffs(val) - 1;
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if (val && (priv->flags & CLK_MUX_INDEX_ONE))
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val--;
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if (val >= priv->parents.count)
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return -EINVAL;
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return val;
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}
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static int clk_ti_mux_set_parent(struct clk *clk, struct clk *parent)
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{
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struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
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int index;
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u32 val;
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index = clk_ti_mux_get_parent_index(&priv->parents, parent);
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if (index < 0) {
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dev_err(clk->dev, "failed to get parent clock\n");
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return index;
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}
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index = clk_mux_index_to_val(NULL, priv->flags, index);
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if (priv->flags & CLK_MUX_HIWORD_MASK) {
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val = priv->mask << (priv->shift + 16);
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} else {
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val = clk_ti_readl(&priv->reg);
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val &= ~(priv->mask << priv->shift);
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}
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val |= index << priv->shift;
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clk_ti_writel(val, &priv->reg);
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clk_ti_latch(&priv->reg, priv->latch);
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return 0;
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}
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static ulong clk_ti_mux_set_rate(struct clk *clk, ulong rate)
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{
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struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
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struct clk *parent;
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int index;
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if ((clk->flags & CLK_SET_RATE_PARENT) == 0)
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return -ENOSYS;
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index = clk_ti_mux_get_index(clk);
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parent = clk_ti_mux_get_parent_by_index(&priv->parents, index);
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if (IS_ERR(parent))
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return PTR_ERR(parent);
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rate = clk_set_rate(parent, rate);
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dev_dbg(clk->dev, "rate=%ld\n", rate);
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return rate;
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}
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static ulong clk_ti_mux_get_rate(struct clk *clk)
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{
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struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
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int index;
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struct clk *parent;
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ulong rate;
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index = clk_ti_mux_get_index(clk);
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parent = clk_ti_mux_get_parent_by_index(&priv->parents, index);
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if (IS_ERR(parent))
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return PTR_ERR(parent);
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rate = clk_get_rate(parent);
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dev_dbg(clk->dev, "rate=%ld\n", rate);
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return rate;
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}
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static ulong clk_ti_mux_round_rate(struct clk *clk, ulong rate)
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{
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struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
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struct clk *parent;
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int index;
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if ((clk->flags & CLK_SET_RATE_PARENT) == 0)
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return -ENOSYS;
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index = clk_ti_mux_get_index(clk);
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parent = clk_ti_mux_get_parent_by_index(&priv->parents, index);
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if (IS_ERR(parent))
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return PTR_ERR(parent);
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rate = clk_round_rate(parent, rate);
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dev_dbg(clk->dev, "rate=%ld\n", rate);
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return rate;
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}
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static int clk_ti_mux_request(struct clk *clk)
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{
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struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
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struct clk *parent;
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int index;
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clk->flags = priv->flags;
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index = clk_ti_mux_get_index(clk);
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parent = clk_ti_mux_get_parent_by_index(&priv->parents, index);
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if (IS_ERR(parent))
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return PTR_ERR(parent);
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return clk_ti_mux_set_parent(clk, parent);
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}
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static struct clk_ops clk_ti_mux_ops = {
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.request = clk_ti_mux_request,
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.round_rate = clk_ti_mux_round_rate,
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.get_rate = clk_ti_mux_get_rate,
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.set_rate = clk_ti_mux_set_rate,
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.set_parent = clk_ti_mux_set_parent,
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};
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static int clk_ti_mux_remove(struct udevice *dev)
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{
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struct clk_ti_mux_priv *priv = dev_get_priv(dev);
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int err;
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err = clk_release_all(priv->parents.clks, priv->parents.count);
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if (err)
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dev_dbg(dev, "could not release all parents' clocks\n");
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return err;
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}
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static int clk_ti_mux_probe(struct udevice *dev)
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{
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struct clk_ti_mux_priv *priv = dev_get_priv(dev);
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int err;
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err = clk_get_bulk(dev, &priv->parents);
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if (err || priv->parents.count < 2) {
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dev_err(dev, "mux-clock must have parents\n");
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return err ? err : -EFAULT;
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}
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/* Generate bit-mask based on parents info */
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priv->mask = priv->parents.count;
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if (!(priv->mux_flags & CLK_MUX_INDEX_ONE))
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priv->mask--;
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priv->mask = (1 << fls(priv->mask)) - 1;
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return 0;
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}
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static int clk_ti_mux_of_to_plat(struct udevice *dev)
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{
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struct clk_ti_mux_priv *priv = dev_get_priv(dev);
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int err;
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err = clk_ti_get_reg_addr(dev, 0, &priv->reg);
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if (err) {
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dev_err(dev, "failed to get register address\n");
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return err;
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}
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priv->shift = dev_read_u32_default(dev, "ti,bit-shift", 0);
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priv->latch = dev_read_s32_default(dev, "ti,latch-bit", -EINVAL);
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priv->flags = CLK_SET_RATE_NO_REPARENT;
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if (dev_read_bool(dev, "ti,set-rate-parent"))
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priv->flags |= CLK_SET_RATE_PARENT;
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if (dev_read_bool(dev, "ti,index-starts-at-one"))
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priv->mux_flags |= CLK_MUX_INDEX_ONE;
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return 0;
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}
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static const struct udevice_id clk_ti_mux_of_match[] = {
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{.compatible = "ti,mux-clock"},
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{},
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};
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U_BOOT_DRIVER(clk_ti_mux) = {
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.name = "ti_mux_clock",
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.id = UCLASS_CLK,
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.of_match = clk_ti_mux_of_match,
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.of_to_plat = clk_ti_mux_of_to_plat,
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.probe = clk_ti_mux_probe,
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.remove = clk_ti_mux_remove,
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.priv_auto = sizeof(struct clk_ti_mux_priv),
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.ops = &clk_ti_mux_ops,
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};
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