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d6cb09d89d
Some devices enumerate various clocks in their DT, and many drivers just blanketly try to enable all of them. This creates problems since we only model a few gate clocks, and the clock driver outputs a warning when a clock is not described: ========= sunxi_set_gate: (CLK#3) unhandled ========= Some clocks don't have an enable bit, or are already enabled in a different way, so we might want to just ignore them. Add a CCU_CLK_F_DUMMY_GATE flag that indicates that case, and define a GATE_DUMMY macro that can be used in the clock description array. Define a few clocks, used by some pinctrl devices, that way to suppress the runtime warnings. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
118 lines
3.2 KiB
C
118 lines
3.2 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2018 Amarula Solutions.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <clk/sunxi.h>
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#include <dt-bindings/clock/sun50i-h6-ccu.h>
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#include <dt-bindings/reset/sun50i-h6-ccu.h>
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#include <linux/bitops.h>
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static struct ccu_clk_gate h6_gates[] = {
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[CLK_PLL_PERIPH0] = GATE(0x020, BIT(31)),
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[CLK_APB1] = GATE_DUMMY,
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[CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
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[CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
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[CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
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[CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
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[CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
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[CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
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[CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
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[CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
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[CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
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[CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
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[CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
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[CLK_SPI0] = GATE(0x940, BIT(31)),
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[CLK_SPI1] = GATE(0x944, BIT(31)),
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[CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
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[CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
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[CLK_BUS_EMAC] = GATE(0x97c, BIT(0)),
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[CLK_USB_PHY0] = GATE(0xa70, BIT(29)),
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[CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
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[CLK_USB_PHY1] = GATE(0xa74, BIT(29)),
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[CLK_USB_HSIC] = GATE(0xa7c, BIT(26)),
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[CLK_USB_HSIC_12M] = GATE(0xa7c, BIT(27)),
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[CLK_USB_PHY3] = GATE(0xa7c, BIT(29)),
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[CLK_USB_OHCI3] = GATE(0xa7c, BIT(31)),
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[CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
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[CLK_BUS_OHCI3] = GATE(0xa8c, BIT(3)),
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[CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
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[CLK_BUS_XHCI] = GATE(0xa8c, BIT(5)),
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[CLK_BUS_EHCI3] = GATE(0xa8c, BIT(7)),
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[CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
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};
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static struct ccu_reset h6_resets[] = {
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[RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
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[RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
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[RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
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[RST_BUS_UART0] = RESET(0x90c, BIT(16)),
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[RST_BUS_UART1] = RESET(0x90c, BIT(17)),
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[RST_BUS_UART2] = RESET(0x90c, BIT(18)),
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[RST_BUS_UART3] = RESET(0x90c, BIT(19)),
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[RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
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[RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
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[RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
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[RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
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[RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
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[RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
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[RST_BUS_EMAC] = RESET(0x97c, BIT(16)),
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[RST_USB_PHY0] = RESET(0xa70, BIT(30)),
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[RST_USB_PHY1] = RESET(0xa74, BIT(30)),
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[RST_USB_HSIC] = RESET(0xa7c, BIT(28)),
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[RST_USB_PHY3] = RESET(0xa7c, BIT(30)),
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[RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
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[RST_BUS_OHCI3] = RESET(0xa8c, BIT(19)),
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[RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
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[RST_BUS_XHCI] = RESET(0xa8c, BIT(21)),
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[RST_BUS_EHCI3] = RESET(0xa8c, BIT(23)),
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[RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
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};
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static const struct ccu_desc h6_ccu_desc = {
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.gates = h6_gates,
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.resets = h6_resets,
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};
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static int h6_clk_bind(struct udevice *dev)
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{
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return sunxi_reset_bind(dev, ARRAY_SIZE(h6_resets));
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}
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static const struct udevice_id h6_ccu_ids[] = {
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{ .compatible = "allwinner,sun50i-h6-ccu",
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.data = (ulong)&h6_ccu_desc },
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{ }
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};
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U_BOOT_DRIVER(clk_sun50i_h6) = {
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.name = "sun50i_h6_ccu",
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.id = UCLASS_CLK,
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.of_match = h6_ccu_ids,
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.priv_auto = sizeof(struct ccu_priv),
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.ops = &sunxi_clk_ops,
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.probe = sunxi_clk_probe,
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.bind = h6_clk_bind,
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};
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