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Import cvmx-sriomaintx-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
61 lines
1.7 KiB
C
61 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#ifndef __CVMX_SRIOMAINTX_DEFS_H__
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#define __CVMX_SRIOMAINTX_DEFS_H__
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static inline u64 CVMX_SRIOMAINTX_PORT_0_CTL2(unsigned long offset)
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{
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switch (cvmx_get_octeon_family()) {
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case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
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return 0x0000010000000154ull + (offset) * 0x100000000ull;
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case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
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return 0x0000000000000154ull;
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case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
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return 0x0000000000000154ull + (offset) * 0x100000000ull;
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}
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return 0x0000010000000154ull + (offset) * 0x100000000ull;
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}
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/**
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* cvmx_sriomaint#_port_0_ctl2
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*
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* These registers are accessed when a local processor or an external
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* device wishes to examine the port baudrate information. The automatic
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* baud rate feature is not available on this device. The SUP_* and ENB_*
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* fields are set directly by the SRIO()_STATUS_REG[SPD] bits as a
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* reference but otherwise have no effect.
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*
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* WARNING!! Writes to this register will reinitialize the SRIO link.
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*/
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union cvmx_sriomaintx_port_0_ctl2 {
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u32 u32;
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struct cvmx_sriomaintx_port_0_ctl2_s {
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u32 sel_baud : 4;
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u32 baud_sup : 1;
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u32 baud_enb : 1;
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u32 sup_125g : 1;
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u32 enb_125g : 1;
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u32 sup_250g : 1;
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u32 enb_250g : 1;
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u32 sup_312g : 1;
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u32 enb_312g : 1;
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u32 sub_500g : 1;
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u32 enb_500g : 1;
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u32 sup_625g : 1;
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u32 enb_625g : 1;
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u32 reserved_2_15 : 14;
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u32 tx_emph : 1;
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u32 emph_en : 1;
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} s;
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struct cvmx_sriomaintx_port_0_ctl2_s cn63xx;
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struct cvmx_sriomaintx_port_0_ctl2_s cn63xxp1;
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struct cvmx_sriomaintx_port_0_ctl2_s cn66xx;
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struct cvmx_sriomaintx_port_0_ctl2_s cnf75xx;
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};
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typedef union cvmx_sriomaintx_port_0_ctl2 cvmx_sriomaintx_port_0_ctl2_t;
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#endif
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