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fe3334d0a3
Import misc remaining header files from 2013 U-Boot. These will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
441 lines
14 KiB
C
441 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*
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* Support functions for managing command queues used for
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* various hardware blocks.
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*
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* The common command queue infrastructure abstracts out the
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* software necessary for adding to Octeon's chained queue
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* structures. These structures are used for commands to the
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* PKO, ZIP, DFA, RAID, HNA, and DMA engine blocks. Although each
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* hardware unit takes commands and CSRs of different types,
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* they all use basic linked command buffers to store the
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* pending request. In general, users of the CVMX API don't
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* call cvmx-cmd-queue functions directly. Instead the hardware
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* unit specific wrapper should be used. The wrappers perform
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* unit specific validation and CSR writes to submit the
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* commands.
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*
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* Even though most software will never directly interact with
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* cvmx-cmd-queue, knowledge of its internal workings can help
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* in diagnosing performance problems and help with debugging.
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*
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* Command queue pointers are stored in a global named block
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* called "cvmx_cmd_queues". Except for the PKO queues, each
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* hardware queue is stored in its own cache line to reduce SMP
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* contention on spin locks. The PKO queues are stored such that
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* every 16th queue is next to each other in memory. This scheme
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* allows for queues being in separate cache lines when there
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* are low number of queues per port. With 16 queues per port,
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* the first queue for each port is in the same cache area. The
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* second queues for each port are in another area, etc. This
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* allows software to implement very efficient lockless PKO with
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* 16 queues per port using a minimum of cache lines per core.
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* All queues for a given core will be isolated in the same
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* cache area.
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*
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* In addition to the memory pointer layout, cvmx-cmd-queue
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* provides an optimized fair ll/sc locking mechanism for the
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* queues. The lock uses a "ticket / now serving" model to
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* maintain fair order on contended locks. In addition, it uses
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* predicted locking time to limit cache contention. When a core
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* know it must wait in line for a lock, it spins on the
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* internal cycle counter to completely eliminate any causes of
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* bus traffic.
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*/
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#ifndef __CVMX_CMD_QUEUE_H__
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#define __CVMX_CMD_QUEUE_H__
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/**
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* By default we disable the max depth support. Most programs
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* don't use it and it slows down the command queue processing
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* significantly.
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*/
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#ifndef CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH
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#define CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH 0
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#endif
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/**
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* Enumeration representing all hardware blocks that use command
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* queues. Each hardware block has up to 65536 sub identifiers for
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* multiple command queues. Not all chips support all hardware
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* units.
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*/
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typedef enum {
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CVMX_CMD_QUEUE_PKO_BASE = 0x00000,
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#define CVMX_CMD_QUEUE_PKO(queue) \
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((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_PKO_BASE + (0xffff & (queue))))
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CVMX_CMD_QUEUE_ZIP = 0x10000,
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#define CVMX_CMD_QUEUE_ZIP_QUE(queue) \
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((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_ZIP + (0xffff & (queue))))
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CVMX_CMD_QUEUE_DFA = 0x20000,
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CVMX_CMD_QUEUE_RAID = 0x30000,
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CVMX_CMD_QUEUE_DMA_BASE = 0x40000,
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#define CVMX_CMD_QUEUE_DMA(queue) \
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((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_DMA_BASE + (0xffff & (queue))))
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CVMX_CMD_QUEUE_BCH = 0x50000,
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#define CVMX_CMD_QUEUE_BCH(queue) ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_BCH + (0xffff & (queue))))
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CVMX_CMD_QUEUE_HNA = 0x60000,
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CVMX_CMD_QUEUE_END = 0x70000,
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} cvmx_cmd_queue_id_t;
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#define CVMX_CMD_QUEUE_ZIP3_QUE(node, queue) \
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((cvmx_cmd_queue_id_t)((node) << 24 | CVMX_CMD_QUEUE_ZIP | (0xffff & (queue))))
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/**
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* Command write operations can fail if the command queue needs
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* a new buffer and the associated FPA pool is empty. It can also
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* fail if the number of queued command words reaches the maximum
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* set at initialization.
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*/
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typedef enum {
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CVMX_CMD_QUEUE_SUCCESS = 0,
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CVMX_CMD_QUEUE_NO_MEMORY = -1,
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CVMX_CMD_QUEUE_FULL = -2,
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CVMX_CMD_QUEUE_INVALID_PARAM = -3,
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CVMX_CMD_QUEUE_ALREADY_SETUP = -4,
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} cvmx_cmd_queue_result_t;
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typedef struct {
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/* First 64-bit word: */
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u64 fpa_pool : 16;
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u64 base_paddr : 48;
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s32 index;
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u16 max_depth;
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u16 pool_size_m1;
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} __cvmx_cmd_queue_state_t;
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/**
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* command-queue locking uses a fair ticket spinlock algo,
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* with 64-bit tickets for endianness-neutrality and
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* counter overflow protection.
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* Lock is free when both counters are of equal value.
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*/
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typedef struct {
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u64 ticket;
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u64 now_serving;
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} __cvmx_cmd_queue_lock_t;
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/**
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* @INTERNAL
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* This structure contains the global state of all command queues.
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* It is stored in a bootmem named block and shared by all
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* applications running on Octeon. Tickets are stored in a different
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* cache line that queue information to reduce the contention on the
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* ll/sc used to get a ticket. If this is not the case, the update
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* of queue state causes the ll/sc to fail quite often.
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*/
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typedef struct {
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__cvmx_cmd_queue_lock_t lock[(CVMX_CMD_QUEUE_END >> 16) * 256];
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__cvmx_cmd_queue_state_t state[(CVMX_CMD_QUEUE_END >> 16) * 256];
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} __cvmx_cmd_queue_all_state_t;
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extern __cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptrs[CVMX_MAX_NODES];
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/**
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* @INTERNAL
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* Internal function to handle the corner cases
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* of adding command words to a queue when the current
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* block is getting full.
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*/
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cvmx_cmd_queue_result_t __cvmx_cmd_queue_write_raw(cvmx_cmd_queue_id_t queue_id,
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__cvmx_cmd_queue_state_t *qptr, int cmd_count,
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const u64 *cmds);
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/**
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* Initialize a command queue for use. The initial FPA buffer is
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* allocated and the hardware unit is configured to point to the
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* new command queue.
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*
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* @param queue_id Hardware command queue to initialize.
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* @param max_depth Maximum outstanding commands that can be queued.
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* @param fpa_pool FPA pool the command queues should come from.
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* @param pool_size Size of each buffer in the FPA pool (bytes)
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*
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* @return CVMX_CMD_QUEUE_SUCCESS or a failure code
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*/
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cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id, int max_depth,
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int fpa_pool, int pool_size);
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/**
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* Shutdown a queue a free it's command buffers to the FPA. The
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* hardware connected to the queue must be stopped before this
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* function is called.
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*
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* @param queue_id Queue to shutdown
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*
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* @return CVMX_CMD_QUEUE_SUCCESS or a failure code
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*/
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cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id);
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/**
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* Return the number of command words pending in the queue. This
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* function may be relatively slow for some hardware units.
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*
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* @param queue_id Hardware command queue to query
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*
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* @return Number of outstanding commands
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*/
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int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id);
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/**
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* Return the command buffer to be written to. The purpose of this
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* function is to allow CVMX routine access to the low level buffer
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* for initial hardware setup. User applications should not call this
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* function directly.
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*
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* @param queue_id Command queue to query
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*
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* @return Command buffer or NULL on failure
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*/
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void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id);
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/**
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* @INTERNAL
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* Retrieve or allocate command queue state named block
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*/
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cvmx_cmd_queue_result_t __cvmx_cmd_queue_init_state_ptr(unsigned int node);
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/**
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* @INTERNAL
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* Get the index into the state arrays for the supplied queue id.
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*
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* @param queue_id Queue ID to get an index for
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*
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* @return Index into the state arrays
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*/
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static inline unsigned int __cvmx_cmd_queue_get_index(cvmx_cmd_queue_id_t queue_id)
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{
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/* Warning: This code currently only works with devices that have 256
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* queues or less. Devices with more than 16 queues are laid out in
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* memory to allow cores quick access to every 16th queue. This reduces
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* cache thrashing when you are running 16 queues per port to support
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* lockless operation
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*/
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unsigned int unit = (queue_id >> 16) & 0xff;
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unsigned int q = (queue_id >> 4) & 0xf;
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unsigned int core = queue_id & 0xf;
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return (unit << 8) | (core << 4) | q;
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}
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static inline int __cvmx_cmd_queue_get_node(cvmx_cmd_queue_id_t queue_id)
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{
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unsigned int node = queue_id >> 24;
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return node;
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}
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/**
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* @INTERNAL
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* Lock the supplied queue so nobody else is updating it at the same
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* time as us.
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*
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* @param queue_id Queue ID to lock
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*
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*/
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static inline void __cvmx_cmd_queue_lock(cvmx_cmd_queue_id_t queue_id)
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{
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}
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/**
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* @INTERNAL
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* Unlock the queue, flushing all writes.
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*
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* @param queue_id Queue ID to lock
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*
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*/
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static inline void __cvmx_cmd_queue_unlock(cvmx_cmd_queue_id_t queue_id)
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{
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CVMX_SYNCWS; /* nudge out the unlock. */
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}
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/**
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* @INTERNAL
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* Initialize a command-queue lock to "unlocked" state.
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*/
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static inline void __cvmx_cmd_queue_lock_init(cvmx_cmd_queue_id_t queue_id)
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{
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unsigned int index = __cvmx_cmd_queue_get_index(queue_id);
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unsigned int node = __cvmx_cmd_queue_get_node(queue_id);
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__cvmx_cmd_queue_state_ptrs[node]->lock[index] = (__cvmx_cmd_queue_lock_t){ 0, 0 };
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CVMX_SYNCWS;
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}
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/**
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* @INTERNAL
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* Get the queue state structure for the given queue id
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*
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* @param queue_id Queue id to get
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*
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* @return Queue structure or NULL on failure
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*/
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static inline __cvmx_cmd_queue_state_t *__cvmx_cmd_queue_get_state(cvmx_cmd_queue_id_t queue_id)
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{
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unsigned int index;
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unsigned int node;
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__cvmx_cmd_queue_state_t *qptr;
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node = __cvmx_cmd_queue_get_node(queue_id);
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index = __cvmx_cmd_queue_get_index(queue_id);
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if (cvmx_unlikely(!__cvmx_cmd_queue_state_ptrs[node]))
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__cvmx_cmd_queue_init_state_ptr(node);
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qptr = &__cvmx_cmd_queue_state_ptrs[node]->state[index];
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return qptr;
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}
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/**
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* Write an arbitrary number of command words to a command queue.
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* This is a generic function; the fixed number of command word
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* functions yield higher performance.
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*
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* @param queue_id Hardware command queue to write to
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* @param use_locking
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* Use internal locking to ensure exclusive access for queue
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* updates. If you don't use this locking you must ensure
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* exclusivity some other way. Locking is strongly recommended.
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* @param cmd_count Number of command words to write
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* @param cmds Array of commands to write
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*
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* @return CVMX_CMD_QUEUE_SUCCESS or a failure code
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*/
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static inline cvmx_cmd_queue_result_t
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cvmx_cmd_queue_write(cvmx_cmd_queue_id_t queue_id, bool use_locking, int cmd_count, const u64 *cmds)
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{
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cvmx_cmd_queue_result_t ret = CVMX_CMD_QUEUE_SUCCESS;
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u64 *cmd_ptr;
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__cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
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/* Make sure nobody else is updating the same queue */
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if (cvmx_likely(use_locking))
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__cvmx_cmd_queue_lock(queue_id);
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/* Most of the time there is lots of free words in current block */
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if (cvmx_unlikely((qptr->index + cmd_count) >= qptr->pool_size_m1)) {
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/* The rare case when nearing end of block */
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ret = __cvmx_cmd_queue_write_raw(queue_id, qptr, cmd_count, cmds);
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} else {
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cmd_ptr = (u64 *)cvmx_phys_to_ptr((u64)qptr->base_paddr);
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/* Loop easy for compiler to unroll for the likely case */
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while (cmd_count > 0) {
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cmd_ptr[qptr->index++] = *cmds++;
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cmd_count--;
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}
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}
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/* All updates are complete. Release the lock and return */
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if (cvmx_likely(use_locking))
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__cvmx_cmd_queue_unlock(queue_id);
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else
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CVMX_SYNCWS;
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return ret;
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}
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/**
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* Simple function to write two command words to a command queue.
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*
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* @param queue_id Hardware command queue to write to
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* @param use_locking
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* Use internal locking to ensure exclusive access for queue
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* updates. If you don't use this locking you must ensure
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* exclusivity some other way. Locking is strongly recommended.
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* @param cmd1 Command
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* @param cmd2 Command
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*
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* @return CVMX_CMD_QUEUE_SUCCESS or a failure code
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*/
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static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write2(cvmx_cmd_queue_id_t queue_id,
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bool use_locking, u64 cmd1, u64 cmd2)
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{
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cvmx_cmd_queue_result_t ret = CVMX_CMD_QUEUE_SUCCESS;
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u64 *cmd_ptr;
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__cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
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/* Make sure nobody else is updating the same queue */
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if (cvmx_likely(use_locking))
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__cvmx_cmd_queue_lock(queue_id);
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if (cvmx_unlikely((qptr->index + 2) >= qptr->pool_size_m1)) {
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/* The rare case when nearing end of block */
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u64 cmds[2];
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cmds[0] = cmd1;
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cmds[1] = cmd2;
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ret = __cvmx_cmd_queue_write_raw(queue_id, qptr, 2, cmds);
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} else {
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/* Likely case to work fast */
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cmd_ptr = (u64 *)cvmx_phys_to_ptr((u64)qptr->base_paddr);
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cmd_ptr += qptr->index;
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qptr->index += 2;
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cmd_ptr[0] = cmd1;
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cmd_ptr[1] = cmd2;
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}
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/* All updates are complete. Release the lock and return */
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if (cvmx_likely(use_locking))
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__cvmx_cmd_queue_unlock(queue_id);
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else
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CVMX_SYNCWS;
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return ret;
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}
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/**
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* Simple function to write three command words to a command queue.
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*
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* @param queue_id Hardware command queue to write to
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* @param use_locking
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* Use internal locking to ensure exclusive access for queue
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* updates. If you don't use this locking you must ensure
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* exclusivity some other way. Locking is strongly recommended.
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* @param cmd1 Command
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* @param cmd2 Command
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* @param cmd3 Command
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*
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* @return CVMX_CMD_QUEUE_SUCCESS or a failure code
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*/
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static inline cvmx_cmd_queue_result_t
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cvmx_cmd_queue_write3(cvmx_cmd_queue_id_t queue_id, bool use_locking, u64 cmd1, u64 cmd2, u64 cmd3)
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{
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cvmx_cmd_queue_result_t ret = CVMX_CMD_QUEUE_SUCCESS;
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__cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
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u64 *cmd_ptr;
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/* Make sure nobody else is updating the same queue */
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if (cvmx_likely(use_locking))
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__cvmx_cmd_queue_lock(queue_id);
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if (cvmx_unlikely((qptr->index + 3) >= qptr->pool_size_m1)) {
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/* Most of the time there is lots of free words in current block */
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u64 cmds[3];
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cmds[0] = cmd1;
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cmds[1] = cmd2;
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cmds[2] = cmd3;
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ret = __cvmx_cmd_queue_write_raw(queue_id, qptr, 3, cmds);
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} else {
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cmd_ptr = (u64 *)cvmx_phys_to_ptr((u64)qptr->base_paddr);
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cmd_ptr += qptr->index;
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qptr->index += 3;
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cmd_ptr[0] = cmd1;
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cmd_ptr[1] = cmd2;
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cmd_ptr[2] = cmd3;
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}
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/* All updates are complete. Release the lock and return */
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if (cvmx_likely(use_locking))
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__cvmx_cmd_queue_unlock(queue_id);
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else
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CVMX_SYNCWS;
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return ret;
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}
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#endif /* __CVMX_CMD_QUEUE_H__ */
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