mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-19 03:08:31 +00:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
147 lines
3.6 KiB
C
147 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#include <common.h>
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#include <i2c.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include "ddr3_init.h"
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#define REG_READ_DATA_SAMPLE_DELAYS_ADDR 0x1538
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#define REG_READ_DATA_SAMPLE_DELAYS_MASK 0x1f
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#define REG_READ_DATA_SAMPLE_DELAYS_OFFS 8
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#define REG_READ_DATA_READY_DELAYS_ADDR 0x153c
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#define REG_READ_DATA_READY_DELAYS_MASK 0x1f
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#define REG_READ_DATA_READY_DELAYS_OFFS 8
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int ddr3_if_ecc_enabled(void)
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{
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struct hws_topology_map *tm = ddr3_get_topology_map();
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if (DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask) ||
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DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))
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return 1;
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else
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return 0;
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}
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int ddr3_pre_algo_config(void)
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{
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struct hws_topology_map *tm = ddr3_get_topology_map();
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/* Set Bus3 ECC training mode */
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if (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask)) {
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/* Set Bus3 ECC MUX */
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CHECK_STATUS(ddr3_tip_if_write
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(0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
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REG_SDRAM_PINS_MUX, 0x100, 0x100));
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}
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/* Set regular ECC training mode (bus4 and bus 3) */
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if ((DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask)) ||
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(DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))) {
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/* Enable ECC Write MUX */
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CHECK_STATUS(ddr3_tip_if_write
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(0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
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TRAINING_SW_2_REG, 0x100, 0x100));
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/* General ECC enable */
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CHECK_STATUS(ddr3_tip_if_write
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(0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
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REG_SDRAM_CONFIG_ADDR, 0x40000, 0x40000));
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/* Disable Read Data ECC MUX */
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CHECK_STATUS(ddr3_tip_if_write
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(0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
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TRAINING_SW_2_REG, 0x0, 0x2));
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}
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return MV_OK;
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}
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int ddr3_post_algo_config(void)
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{
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struct hws_topology_map *tm = ddr3_get_topology_map();
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int status;
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status = ddr3_post_run_alg();
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if (MV_OK != status) {
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printf("DDR3 Post Run Alg - FAILED 0x%x\n", status);
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return status;
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}
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/* Un_set ECC training mode */
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if ((DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask)) ||
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(DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask))) {
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/* Disable ECC Write MUX */
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CHECK_STATUS(ddr3_tip_if_write
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(0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
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TRAINING_SW_2_REG, 0x0, 0x100));
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/* General ECC and Bus3 ECC MUX remains enabled */
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}
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return MV_OK;
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}
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int ddr3_hws_hw_training(void)
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{
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enum hws_algo_type algo_mode = ALGO_TYPE_DYNAMIC;
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int status;
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struct init_cntr_param init_param;
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status = ddr3_silicon_pre_init();
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if (MV_OK != status) {
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printf("DDR3 Pre silicon Config - FAILED 0x%x\n", status);
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return status;
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}
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init_param.do_mrs_phy = 1;
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#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
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init_param.is_ctrl64_bit = 0;
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#else
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init_param.is_ctrl64_bit = 1;
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#endif
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#if defined(CONFIG_ALLEYCAT3) || defined(CONFIG_ARMADA_38X) || \
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defined(CONFIG_ARMADA_39X)
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init_param.init_phy = 1;
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#else
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init_param.init_phy = 0;
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#endif
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init_param.msys_init = 1;
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status = hws_ddr3_tip_init_controller(0, &init_param);
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if (MV_OK != status) {
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printf("DDR3 init controller - FAILED 0x%x\n", status);
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return status;
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}
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status = ddr3_silicon_post_init();
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if (MV_OK != status) {
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printf("DDR3 Post Init - FAILED 0x%x\n", status);
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return status;
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}
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status = ddr3_pre_algo_config();
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if (MV_OK != status) {
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printf("DDR3 Pre Algo Config - FAILED 0x%x\n", status);
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return status;
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}
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/* run algorithm in order to configure the PHY */
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status = hws_ddr3_tip_run_alg(0, algo_mode);
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if (MV_OK != status) {
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printf("DDR3 run algorithm - FAILED 0x%x\n", status);
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return status;
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}
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status = ddr3_post_algo_config();
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if (MV_OK != status) {
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printf("DDR3 Post Algo Config - FAILED 0x%x\n", status);
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return status;
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}
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return MV_OK;
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}
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