mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
92 lines
2.8 KiB
C
92 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _DDR3_A38X_H
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#define _DDR3_A38X_H
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#define MAX_INTERFACE_NUM 1
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#define MAX_BUS_NUM 5
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#include "ddr3_hws_hw_training_def.h"
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#define ECC_SUPPORT
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/* right now, we're not supporting this in mainline */
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#undef SUPPORT_STATIC_DUNIT_CONFIG
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/* Controler bus divider 1 for 32 bit, 2 for 64 bit */
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#define DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER 1
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/* Tune internal training params values */
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#define TUNE_TRAINING_PARAMS_CK_DELAY 160
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#define TUNE_TRAINING_PARAMS_CK_DELAY_16 160
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#define TUNE_TRAINING_PARAMS_PFINGER 41
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#define TUNE_TRAINING_PARAMS_NFINGER 43
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#define TUNE_TRAINING_PARAMS_PHYREG3VAL 0xa
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#define MARVELL_BOARD MARVELL_BOARD_ID_BASE
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#define REG_DEVICE_SAR1_ADDR 0xe4204
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#define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET 17
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#define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK 0x1f
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/* DRAM Windows */
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#define REG_XBAR_WIN_5_CTRL_ADDR 0x20050
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#define REG_XBAR_WIN_5_BASE_ADDR 0x20054
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/* DRAM Windows */
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#define REG_XBAR_WIN_4_CTRL_ADDR 0x20040
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#define REG_XBAR_WIN_4_BASE_ADDR 0x20044
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#define REG_XBAR_WIN_4_REMAP_ADDR 0x20048
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#define REG_XBAR_WIN_7_REMAP_ADDR 0x20078
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#define REG_XBAR_WIN_16_CTRL_ADDR 0x200d0
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#define REG_XBAR_WIN_16_BASE_ADDR 0x200d4
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#define REG_XBAR_WIN_16_REMAP_ADDR 0x200dc
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#define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8
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#define REG_FASTPATH_WIN_BASE_ADDR(win) (0x20180 + (0x8 * win))
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#define REG_FASTPATH_WIN_CTRL_ADDR(win) (0x20184 + (0x8 * win))
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/* SatR defined too change topology busWidth and ECC configuration */
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#define DDR_SATR_CONFIG_MASK_WIDTH 0x8
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#define DDR_SATR_CONFIG_MASK_ECC 0x10
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#define DDR_SATR_CONFIG_MASK_ECC_PUP 0x20
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#define REG_SAMPLE_RESET_HIGH_ADDR 0x18600
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#define MV_BOARD_REFCLK MV_BOARD_REFCLK_25MHZ
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/* Matrix enables DRAM modes (bus width/ECC) per boardId */
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#define TOPOLOGY_UPDATE_32BIT 0
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#define TOPOLOGY_UPDATE_32BIT_ECC 1
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#define TOPOLOGY_UPDATE_16BIT 2
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#define TOPOLOGY_UPDATE_16BIT_ECC 3
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#define TOPOLOGY_UPDATE_16BIT_ECC_PUP3 4
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#define TOPOLOGY_UPDATE { \
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/* 32Bit, 32bit ECC, 16bit, 16bit ECC PUP4, 16bit ECC PUP3 */ \
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{1, 1, 1, 1, 1}, /* RD_NAS_68XX_ID */ \
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{1, 1, 1, 1, 1}, /* DB_68XX_ID */ \
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{1, 0, 1, 0, 1}, /* RD_AP_68XX_ID */ \
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{1, 0, 1, 0, 1}, /* DB_AP_68XX_ID */ \
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{1, 0, 1, 0, 1}, /* DB_GP_68XX_ID */ \
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{0, 0, 1, 1, 0}, /* DB_BP_6821_ID */ \
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{1, 1, 1, 1, 1} /* DB_AMC_6820_ID */ \
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};
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enum {
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CPU_1066MHZ_DDR_400MHZ,
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CPU_RESERVED_DDR_RESERVED0,
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CPU_667MHZ_DDR_667MHZ,
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CPU_800MHZ_DDR_800MHZ,
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CPU_RESERVED_DDR_RESERVED1,
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CPU_RESERVED_DDR_RESERVED2,
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CPU_RESERVED_DDR_RESERVED3,
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LAST_FREQ
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};
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#define ACTIVE_INTERFACE_MASK 0x1
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#endif /* _DDR3_A38X_H */
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