mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 01:38:22 +00:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
353 lines
9.5 KiB
C
353 lines
9.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include "ctrl_pex.h"
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#include "sys_env_lib.h"
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__weak void board_pex_config(void)
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{
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/* nothing in this weak default implementation */
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}
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int hws_pex_config(const struct serdes_map *serdes_map, u8 count)
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{
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u32 pex_idx, tmp, next_busno, first_busno, temp_pex_reg,
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temp_reg, addr, dev_id, ctrl_mode;
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enum serdes_type serdes_type;
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u32 idx;
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DEBUG_INIT_FULL_S("\n### hws_pex_config ###\n");
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for (idx = 0; idx < count; idx++) {
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serdes_type = serdes_map[idx].serdes_type;
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/* configuration for PEX only */
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if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
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(serdes_type != PEX2) && (serdes_type != PEX3))
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continue;
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if ((serdes_type != PEX0) &&
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((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
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(serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
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/* for PEX by4 - relevant for the first port only */
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continue;
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}
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pex_idx = serdes_type - PEX0;
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tmp = reg_read(PEX_CAPABILITIES_REG(pex_idx));
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tmp &= ~(0xf << 20);
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tmp |= (0x4 << 20);
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reg_write(PEX_CAPABILITIES_REG(pex_idx), tmp);
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}
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tmp = reg_read(SOC_CTRL_REG);
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tmp &= ~0x03;
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for (idx = 0; idx < count; idx++) {
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serdes_type = serdes_map[idx].serdes_type;
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if ((serdes_type != PEX0) &&
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((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
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(serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
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/* for PEX by4 - relevant for the first port only */
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continue;
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}
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switch (serdes_type) {
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case PEX0:
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tmp |= 0x1 << PCIE0_ENABLE_OFFS;
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break;
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case PEX1:
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tmp |= 0x1 << PCIE1_ENABLE_OFFS;
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break;
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case PEX2:
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tmp |= 0x1 << PCIE2_ENABLE_OFFS;
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break;
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case PEX3:
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tmp |= 0x1 << PCIE3_ENABLE_OFFS;
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break;
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default:
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break;
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}
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}
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reg_write(SOC_CTRL_REG, tmp);
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/* Support gen1/gen2 */
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DEBUG_INIT_FULL_S("Support gen1/gen2\n");
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board_pex_config();
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next_busno = 0;
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mdelay(150);
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for (idx = 0; idx < count; idx++) {
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serdes_type = serdes_map[idx].serdes_type;
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DEBUG_INIT_FULL_S(" serdes_type=0x");
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DEBUG_INIT_FULL_D(serdes_type, 8);
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DEBUG_INIT_FULL_S("\n");
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DEBUG_INIT_FULL_S(" idx=0x");
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DEBUG_INIT_FULL_D(idx, 8);
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DEBUG_INIT_FULL_S("\n");
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/* Configuration for PEX only */
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if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
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(serdes_type != PEX2) && (serdes_type != PEX3))
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continue;
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if ((serdes_type != PEX0) &&
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((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
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(serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
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/* for PEX by4 - relevant for the first port only */
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continue;
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}
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pex_idx = serdes_type - PEX0;
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tmp = reg_read(PEX_DBG_STATUS_REG(pex_idx));
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first_busno = next_busno;
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if ((tmp & 0x7f) != 0x7e) {
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DEBUG_INIT_S("PCIe, Idx ");
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DEBUG_INIT_D(pex_idx, 1);
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DEBUG_INIT_S(": detected no link\n");
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continue;
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}
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next_busno++;
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temp_pex_reg = reg_read((PEX_CFG_DIRECT_ACCESS
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(pex_idx, PEX_LINK_CAPABILITY_REG)));
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temp_pex_reg &= 0xf;
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if (temp_pex_reg != 0x2)
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continue;
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temp_reg = (reg_read(PEX_CFG_DIRECT_ACCESS(
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pex_idx,
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PEX_LINK_CTRL_STAT_REG)) &
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0xf0000) >> 16;
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/* Check if the link established is GEN1 */
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DEBUG_INIT_FULL_S
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("Checking if the link established is gen1\n");
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if (temp_reg != 0x1)
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continue;
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pex_local_bus_num_set(pex_idx, first_busno);
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pex_local_dev_num_set(pex_idx, 1);
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DEBUG_INIT_FULL_S("PCIe, Idx ");
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DEBUG_INIT_FULL_D(pex_idx, 1);
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DEBUG_INIT_S(":** Link is Gen1, check the EP capability\n");
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/* link is Gen1, check the EP capability */
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addr = pex_config_read(pex_idx, first_busno, 0, 0, 0x34) & 0xff;
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DEBUG_INIT_FULL_C("pex_config_read: return addr=0x%x", addr, 4);
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if (addr == 0xff) {
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DEBUG_INIT_FULL_C
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("pex_config_read: return 0xff -->PCIe (%d): Detected No Link.",
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pex_idx, 1);
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continue;
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}
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while ((pex_config_read(pex_idx, first_busno, 0, 0, addr)
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& 0xff) != 0x10) {
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addr = (pex_config_read(pex_idx, first_busno, 0,
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0, addr) & 0xff00) >> 8;
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}
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/* Check for Gen2 and above */
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if ((pex_config_read(pex_idx, first_busno, 0, 0,
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addr + 0xc) & 0xf) < 0x2) {
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DEBUG_INIT_S("PCIe, Idx ");
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DEBUG_INIT_D(pex_idx, 1);
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DEBUG_INIT_S(": remains Gen1\n");
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continue;
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}
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tmp = reg_read(PEX_LINK_CTRL_STATUS2_REG(pex_idx));
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DEBUG_RD_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp);
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tmp &= ~(BIT(0) | BIT(1));
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tmp |= BIT(1);
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tmp |= BIT(6); /* Select Deemphasize (-3.5d_b) */
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reg_write(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp);
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DEBUG_WR_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp);
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tmp = reg_read(PEX_CTRL_REG(pex_idx));
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DEBUG_RD_REG(PEX_CTRL_REG(pex_idx), tmp);
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tmp |= BIT(10);
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reg_write(PEX_CTRL_REG(pex_idx), tmp);
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DEBUG_WR_REG(PEX_CTRL_REG(pex_idx), tmp);
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/*
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* We need to wait 10ms before reading the PEX_DBG_STATUS_REG
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* in order not to read the status of the former state
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*/
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mdelay(10);
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DEBUG_INIT_S("PCIe, Idx ");
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DEBUG_INIT_D(pex_idx, 1);
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DEBUG_INIT_S
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(": Link upgraded to Gen2 based on client capabilities\n");
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}
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/* Update pex DEVICE ID */
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ctrl_mode = sys_env_model_get();
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for (idx = 0; idx < count; idx++) {
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serdes_type = serdes_map[idx].serdes_type;
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/* configuration for PEX only */
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if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
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(serdes_type != PEX2) && (serdes_type != PEX3))
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continue;
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if ((serdes_type != PEX0) &&
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((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
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(serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
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/* for PEX by4 - relevant for the first port only */
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continue;
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}
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pex_idx = serdes_type - PEX0;
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dev_id = reg_read(PEX_CFG_DIRECT_ACCESS
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(pex_idx, PEX_DEVICE_AND_VENDOR_ID));
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dev_id &= 0xffff;
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dev_id |= ((ctrl_mode << 16) & 0xffff0000);
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reg_write(PEX_CFG_DIRECT_ACCESS
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(pex_idx, PEX_DEVICE_AND_VENDOR_ID), dev_id);
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}
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DEBUG_INIT_FULL_C("Update PEX Device ID ", ctrl_mode, 4);
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return MV_OK;
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}
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int pex_local_bus_num_set(u32 pex_if, u32 bus_num)
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{
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u32 pex_status;
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DEBUG_INIT_FULL_S("\n### pex_local_bus_num_set ###\n");
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if (bus_num >= MAX_PEX_BUSSES) {
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DEBUG_INIT_C("pex_local_bus_num_set: Illegal bus number %d\n",
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bus_num, 4);
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return MV_BAD_PARAM;
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}
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pex_status = reg_read(PEX_STATUS_REG(pex_if));
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pex_status &= ~PXSR_PEX_BUS_NUM_MASK;
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pex_status |=
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(bus_num << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK;
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reg_write(PEX_STATUS_REG(pex_if), pex_status);
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return MV_OK;
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}
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int pex_local_dev_num_set(u32 pex_if, u32 dev_num)
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{
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u32 pex_status;
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DEBUG_INIT_FULL_S("\n### pex_local_dev_num_set ###\n");
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pex_status = reg_read(PEX_STATUS_REG(pex_if));
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pex_status &= ~PXSR_PEX_DEV_NUM_MASK;
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pex_status |=
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(dev_num << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK;
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reg_write(PEX_STATUS_REG(pex_if), pex_status);
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return MV_OK;
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}
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/*
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* pex_config_read - Read from configuration space
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*
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* DESCRIPTION:
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* This function performs a 32 bit read from PEX configuration space.
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* It supports both type 0 and type 1 of Configuration Transactions
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* (local and over bridge). In order to read from local bus segment, use
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* bus number retrieved from pex_local_bus_num_get(). Other bus numbers
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* will result configuration transaction of type 1 (over bridge).
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*
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* INPUT:
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* pex_if - PEX interface number.
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* bus - PEX segment bus number.
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* dev - PEX device number.
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* func - Function number.
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* reg_offs - Register offset.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* 32bit register data, 0xffffffff on error
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*/
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u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off)
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{
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u32 pex_data = 0;
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u32 local_dev, local_bus;
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u32 pex_status;
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pex_status = reg_read(PEX_STATUS_REG(pex_if));
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local_dev =
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((pex_status & PXSR_PEX_DEV_NUM_MASK) >> PXSR_PEX_DEV_NUM_OFFS);
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local_bus =
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((pex_status & PXSR_PEX_BUS_NUM_MASK) >> PXSR_PEX_BUS_NUM_OFFS);
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/*
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* In PCI Express we have only one device number
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* and this number is the first number we encounter
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* else that the local_dev
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* spec pex define return on config read/write on any device
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*/
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if (bus == local_bus) {
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if (local_dev == 0) {
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/*
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* if local dev is 0 then the first number we encounter
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* after 0 is 1
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*/
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if ((dev != 1) && (dev != local_dev))
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return MV_ERROR;
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} else {
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/*
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* if local dev is not 0 then the first number we
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* encounter is 0
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*/
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if ((dev != 0) && (dev != local_dev))
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return MV_ERROR;
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}
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}
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/* Creating PEX address to be passed */
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pex_data = (bus << PXCAR_BUS_NUM_OFFS);
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pex_data |= (dev << PXCAR_DEVICE_NUM_OFFS);
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pex_data |= (func << PXCAR_FUNC_NUM_OFFS);
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/* Legacy register space */
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pex_data |= (reg_off & PXCAR_REG_NUM_MASK);
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/* Extended register space */
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pex_data |= (((reg_off & PXCAR_REAL_EXT_REG_NUM_MASK) >>
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PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS);
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pex_data |= PXCAR_CONFIG_EN;
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/* Write the address to the PEX configuration address register */
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reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data);
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/*
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* In order to let the PEX controller absorbed the address
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* of the read transaction we perform a validity check that
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* the address was written
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*/
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if (pex_data != reg_read(PEX_CFG_ADDR_REG(pex_if)))
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return MV_ERROR;
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/* Cleaning Master Abort */
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reg_bit_set(PEX_CFG_DIRECT_ACCESS(pex_if, PEX_STATUS_AND_COMMAND),
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PXSAC_MABORT);
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/* Read the Data returned in the PEX Data register */
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pex_data = reg_read(PEX_CFG_DATA_REG(pex_if));
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DEBUG_INIT_FULL_C(" --> ", pex_data, 4);
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return pex_data;
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}
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