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24e8bee508
This patch adds generic codes to support Freescale's Vybrid VF610 CPU. It aligns Vybrid VF610 platform with i.MX platform. As there are some differences between VF610 and i.MX platforms, the specific codes are in the arch/arm/cpu/armv7/vf610 directory. Signed-off-by: Alison Wang <b18965@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
419 lines
13 KiB
C
419 lines
13 KiB
C
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_IMX_REGS_H__
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#define __ASM_ARCH_IMX_REGS_H__
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#define ARCH_MXC
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#define IRAM_BASE_ADDR 0x3F000000 /* internal ram */
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#define IRAM_SIZE 0x00080000 /* 512 KB */
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#define AIPS0_BASE_ADDR 0x40000000
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#define AIPS1_BASE_ADDR 0x40080000
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/* AIPS 0 */
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#define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
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#define MSCM_IR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001800)
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#define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
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#define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000)
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#define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000)
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#define NIC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00008000)
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#define NIC1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00009000)
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#define NIC2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000)
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#define NIC3_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000)
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#define NIC4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000C000)
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#define NIC5_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000)
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#define NIC6_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000E000)
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#define NIC7_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000F000)
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#define AHBTZASC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000)
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#define TZASC_SYS0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00011000)
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#define TZASC_SYS1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00012000)
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#define TZASC_GFX_BASE_ADDR (AIPS0_BASE_ADDR + 0x00013000)
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#define TZASC_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00014000)
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#define TZASC_DDR1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00015000)
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#define CSU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00017000)
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#define DMA0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00018000)
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#define DMA0_TCD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00019000)
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#define SEMA4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001D000)
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#define FB_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001E000)
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#define DMA_MUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00024000)
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#define UART0_BASE (AIPS0_BASE_ADDR + 0x00027000)
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#define UART1_BASE (AIPS0_BASE_ADDR + 0x00028000)
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#define UART2_BASE (AIPS0_BASE_ADDR + 0x00029000)
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#define UART3_BASE (AIPS0_BASE_ADDR + 0x0002A000)
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#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002C000)
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#define SPI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002D000)
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#define SAI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002F000)
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#define SAI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000)
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#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
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#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
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#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000)
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#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
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#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
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#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
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#define FTM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000)
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#define ADC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003B000)
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#define TCON0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003D000)
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#define WDOG1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003E000)
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#define LPTMR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00040000)
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#define RLE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000)
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#define MLB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00043000)
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#define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000)
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#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
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#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000)
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#define SCSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
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#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000)
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#define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000)
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#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
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#define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000)
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#define WDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000)
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#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000)
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#define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000)
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#define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000)
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#define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000)
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#define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000)
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#define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000)
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#define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000)
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/* AIPS 1 */
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#define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000)
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#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000)
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#define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000)
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#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
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#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000)
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/* MUX mode and PAD ctrl are in one register */
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#define CONFIG_IOMUX_SHARE_CONF_REG
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#define FEC_QUIRK_ENET_MAC
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/* MSCM interrupt rounter */
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#define MSCM_IRSPRC_CP0_EN 1
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#define MSCM_IRSPRC_NUM 112
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/* DDRMC */
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#define DDRMC_PHY_DQ_TIMING 0x00002613
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#define DDRMC_PHY_DQS_TIMING 0x00002615
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#define DDRMC_PHY_CTRL 0x01210080
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#define DDRMC_PHY_MASTER_CTRL 0x0001012a
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#define DDRMC_PHY_SLAVE_CTRL 0x00012020
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#define DDRMC_PHY50_DDR3_MODE (1 << 12)
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#define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8)
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#define DDRMC_CR00_DRAM_CLASS_DDR3 (0x6 << 8)
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#define DDRMC_CR00_DRAM_CLASS_LPDDR2 (0x5 << 8)
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#define DDRMC_CR00_START 1
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#define DDRMC_CR02_DRAM_TINIT(v) ((v) & 0xffffff)
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#define DDRMC_CR10_TRST_PWRON(v) (v)
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#define DDRMC_CR11_CKE_INACTIVE(v) (v)
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#define DDRMC_CR12_WRLAT(v) (((v) & 0x1f) << 8)
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#define DDRMC_CR12_CASLAT_LIN(v) ((v) & 0x3f)
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#define DDRMC_CR13_TRC(v) (((v) & 0xff) << 24)
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#define DDRMC_CR13_TRRD(v) (((v) & 0xff) << 16)
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#define DDRMC_CR13_TCCD(v) (((v) & 0x1f) << 8)
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#define DDRMC_CR13_TBST_INT_INTERVAL(v) ((v) & 0x7)
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#define DDRMC_CR14_TFAW(v) (((v) & 0x3f) << 24)
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#define DDRMC_CR14_TRP(v) (((v) & 0x1f) << 16)
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#define DDRMC_CR14_TWTR(v) (((v) & 0xf) << 8)
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#define DDRMC_CR14_TRAS_MIN(v) ((v) & 0xff)
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#define DDRMC_CR16_TMRD(v) (((v) & 0x1f) << 24)
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#define DDRMC_CR16_TRTP(v) (((v) & 0xf) << 16)
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#define DDRMC_CR17_TRAS_MAX(v) (((v) & 0x1ffff) << 8)
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#define DDRMC_CR17_TMOD(v) ((v) & 0xff)
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#define DDRMC_CR18_TCKESR(v) (((v) & 0x1f) << 8)
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#define DDRMC_CR18_TCKE(v) ((v) & 0x7)
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#define DDRMC_CR20_AP_EN (1 << 24)
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#define DDRMC_CR21_TRCD_INT(v) (((v) & 0xff) << 16)
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#define DDRMC_CR21_TRAS_LOCKOUT (1 << 8)
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#define DDRMC_CR21_CCMAP_EN 1
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#define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16)
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#define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24)
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#define DDRMC_CR23_TDLL(v) ((v) & 0xff)
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#define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f)
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#define DDRMC_CR25_TREF_EN (1 << 16)
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#define DDRMC_CR26_TREF(v) (((v) & 0xffff) << 16)
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#define DDRMC_CR26_TRFC(v) ((v) & 0x3ff)
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#define DDRMC_CR28_TREF_INT(v) ((v) & 0xffff)
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#define DDRMC_CR29_TPDEX(v) ((v) & 0xffff)
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#define DDRMC_CR30_TXPDLL(v) ((v) & 0xffff)
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#define DDRMC_CR31_TXSNR(v) (((v) & 0xffff) << 16)
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#define DDRMC_CR31_TXSR(v) ((v) & 0xffff)
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#define DDRMC_CR33_EN_QK_SREF (1 << 16)
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#define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16)
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#define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8)
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#define DDRMC_CR38_FREQ_CHG_EN (1 << 8)
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#define DDRMC_CR39_PHY_INI_COM(v) (((v) & 0xffff) << 16)
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#define DDRMC_CR39_PHY_INI_STA(v) (((v) & 0xff) << 8)
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#define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) & 0x3)
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#define DDRMC_CR41_PHY_INI_STRT_INI_DIS 1
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#define DDRMC_CR48_MR1_DA_0(v) (((v) & 0xffff) << 16)
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#define DDRMC_CR48_MR0_DA_0(v) ((v) & 0xffff)
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#define DDRMC_CR66_ZQCL(v) (((v) & 0xfff) << 16)
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#define DDRMC_CR66_ZQINIT(v) ((v) & 0xfff)
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#define DDRMC_CR67_ZQCS(v) ((v) & 0xfff)
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#define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8)
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#define DDRMC_CR70_REF_PER_ZQ(v) (v)
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#define DDRMC_CR72_ZQCS_ROTATE (1 << 24)
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#define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24)
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#define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << 16)
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#define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << 8)
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#define DDRMC_CR74_BANKSPLT_EN (1 << 24)
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#define DDRMC_CR74_ADDR_CMP_EN (1 << 16)
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#define DDRMC_CR74_CMD_AGE_CNT(v) (((v) & 0xff) << 8)
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#define DDRMC_CR74_AGE_CNT(v) ((v) & 0xff)
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#define DDRMC_CR75_RW_PG_EN (1 << 24)
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#define DDRMC_CR75_RW_EN (1 << 16)
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#define DDRMC_CR75_PRI_EN (1 << 8)
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#define DDRMC_CR75_PLEN 1
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#define DDRMC_CR76_NQENT_ACTDIS(v) (((v) & 0x7) << 24)
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#define DDRMC_CR76_D_RW_G_BKCN(v) (((v) & 0x3) << 16)
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#define DDRMC_CR76_W2R_SPLT_EN (1 << 8)
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#define DDRMC_CR76_CS_EN 1
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#define DDRMC_CR77_CS_MAP (1 << 24)
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#define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8)
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#define DDRMC_CR77_SWAP_EN 1
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#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf)
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#define DDRMC_CR79_CTLUPD_AREF (1 << 24)
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#define DDRMC_CR82_INT_MASK 0x1fffffff
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#define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24)
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#define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16)
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#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16)
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#define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf)
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#define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16)
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#define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8)
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#define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f)
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#define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8)
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#define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff)
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#define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8)
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#define DDRMC_CR117_AXI0_W_PRI(v) (((v) & 0x3) << 8)
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#define DDRMC_CR117_AXI0_R_PRI(v) ((v) & 0x3)
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#define DDRMC_CR118_AXI1_W_PRI(v) (((v) & 0x3) << 24)
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#define DDRMC_CR118_AXI1_R_PRI(v) (((v) & 0x3) << 16)
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#define DDRMC_CR120_AXI0_PRI1_RPRI(v) (((v) & 0xf) << 24)
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#define DDRMC_CR120_AXI0_PRI0_RPRI(v) (((v) & 0xf) << 16)
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#define DDRMC_CR121_AXI0_PRI3_RPRI(v) (((v) & 0xf) << 8)
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#define DDRMC_CR121_AXI0_PRI2_RPRI(v) ((v) & 0xf)
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#define DDRMC_CR122_AXI1_PRI1_RPRI(v) (((v) & 0xf) << 24)
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#define DDRMC_CR122_AXI1_PRI0_RPRI(v) (((v) & 0xf) << 16)
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#define DDRMC_CR122_AXI0_PRIRLX(v) ((v) & 0x3ff)
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#define DDRMC_CR123_AXI1_PRI3_RPRI(v) (((v) & 0xf) << 8)
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#define DDRMC_CR123_AXI1_PRI2_RPRI(v) ((v) & 0xf)
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#define DDRMC_CR124_AXI1_PRIRLX(v) ((v) & 0x3ff)
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#define DDRMC_CR126_PHY_RDLAT(v) (((v) & 0x3f) << 8)
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#define DDRMC_CR132_WRLAT_ADJ(v) (((v) & 0x1f) << 8)
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#define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f)
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#define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24)
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#define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16)
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#define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8)
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#define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff)
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#define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27)
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#define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21)
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#define DDRMC_CR155_AXI0_AWCACHE (1 << 10)
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#define DDRMC_CR155_PAD_ODT_BYTE1(v) ((v) & 0x7)
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#define DDRMC_CR158_TWR(v) ((v) & 0x3f)
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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/* System Reset Controller (SRC) */
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struct src {
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u32 scr;
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u32 sbmr1;
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u32 srsr;
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u32 secr;
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u32 gpsr;
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u32 sicr;
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u32 simr;
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u32 sbmr2;
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u32 gpr0;
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u32 gpr1;
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u32 gpr2;
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u32 gpr3;
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u32 gpr4;
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u32 hab0;
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u32 hab1;
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u32 hab2;
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u32 hab3;
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u32 hab4;
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u32 hab5;
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u32 misc0;
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u32 misc1;
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u32 misc2;
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u32 misc3;
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};
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/* Periodic Interrupt Timer (PIT) */
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struct pit_reg {
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u32 mcr;
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u32 recv0[55];
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u32 ltmr64h;
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u32 ltmr64l;
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u32 recv1[6];
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u32 ldval0;
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u32 cval0;
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u32 tctrl0;
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u32 tflg0;
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u32 ldval1;
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u32 cval1;
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u32 tctrl1;
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u32 tflg1;
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u32 ldval2;
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u32 cval2;
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u32 tctrl2;
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u32 tflg2;
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u32 ldval3;
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u32 cval3;
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u32 tctrl3;
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u32 tflg3;
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u32 ldval4;
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u32 cval4;
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u32 tctrl4;
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u32 tflg4;
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u32 ldval5;
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u32 cval5;
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u32 tctrl5;
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u32 tflg5;
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u32 ldval6;
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u32 cval6;
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u32 tctrl6;
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u32 tflg6;
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u32 ldval7;
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u32 cval7;
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u32 tctrl7;
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u32 tflg7;
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};
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/* Watchdog Timer (WDOG) */
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struct wdog_regs {
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u16 wcr;
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u16 wsr;
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u16 wrsr;
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u16 wicr;
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u16 wmcr;
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};
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/* LPDDR2/DDR3 SDRAM Memory Controller (DDRMC) */
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struct ddrmr_regs {
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u32 cr[162];
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u32 rsvd[94];
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u32 phy[53];
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};
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/* On-Chip One Time Programmable Controller (OCOTP) */
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struct ocotp_regs {
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u32 ctrl;
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u32 ctrl_set;
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u32 ctrl_clr;
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u32 ctrl_tog;
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u32 timing;
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u32 rsvd0[3];
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u32 data;
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u32 rsvd1[3];
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u32 read_ctrl;
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u32 rsvd2[3];
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u32 read_fuse_data;
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u32 rsvd3[7];
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u32 scs;
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u32 scs_set;
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u32 scs_clr;
|
|
u32 scs_tog;
|
|
u32 crc_addr;
|
|
u32 rsvd4[3];
|
|
u32 crc_value;
|
|
u32 rsvd5[3];
|
|
u32 version;
|
|
u32 rsvd6[0xdb];
|
|
|
|
struct fuse_bank {
|
|
u32 fuse_regs[0x20];
|
|
} bank[16];
|
|
};
|
|
|
|
struct fuse_bank0_regs {
|
|
u32 lock;
|
|
u32 rsvd0[3];
|
|
u32 uid_low;
|
|
u32 rsvd1[3];
|
|
u32 uid_high;
|
|
u32 rsvd2[0x17];
|
|
};
|
|
|
|
struct fuse_bank4_regs {
|
|
u32 sjc_resp0;
|
|
u32 rsvd0[3];
|
|
u32 sjc_resp1;
|
|
u32 rsvd1[3];
|
|
u32 mac_addr0;
|
|
u32 rsvd2[3];
|
|
u32 mac_addr1;
|
|
u32 rsvd3[3];
|
|
u32 mac_addr2;
|
|
u32 rsvd4[3];
|
|
u32 mac_addr3;
|
|
u32 rsvd5[3];
|
|
u32 gp1;
|
|
u32 rsvd6[3];
|
|
u32 gp2;
|
|
u32 rsvd7[3];
|
|
};
|
|
|
|
/* UART */
|
|
struct lpuart_fsl {
|
|
u8 ubdh;
|
|
u8 ubdl;
|
|
u8 uc1;
|
|
u8 uc2;
|
|
u8 us1;
|
|
u8 us2;
|
|
u8 uc3;
|
|
u8 ud;
|
|
u8 uma1;
|
|
u8 uma2;
|
|
u8 uc4;
|
|
u8 uc5;
|
|
u8 ued;
|
|
u8 umodem;
|
|
u8 uir;
|
|
u8 reserved;
|
|
u8 upfifo;
|
|
u8 ucfifo;
|
|
u8 usfifo;
|
|
u8 utwfifo;
|
|
u8 utcfifo;
|
|
u8 urwfifo;
|
|
u8 urcfifo;
|
|
u8 rsvd[28];
|
|
};
|
|
|
|
/* MSCM Interrupt Router */
|
|
struct mscm_ir {
|
|
u32 ircp0ir;
|
|
u32 ircp1ir;
|
|
u32 rsvd1[6];
|
|
u32 ircpgir;
|
|
u32 rsvd2[23];
|
|
u16 irsprc[112];
|
|
u16 rsvd3[848];
|
|
};
|
|
|
|
#endif /* __ASSEMBLER__*/
|
|
|
|
#endif /* __ASM_ARCH_IMX_REGS_H__ */
|