Fabio Estevam a307760ab4 mx6sabresd: Simplify the Ethernet PHY configuration ... As per the AR8031 datasheet: "For a reliable power on reset, suggest to keep asserting the reset low long enough (10ms) to ensure the clock is stable and clock-to-reset 1ms requirement is satisfied." So do as suggested and also add a 100us delay after deasserting the reset line to guarantee that the PHY ID can be read correctly and the Atheros 8031 PHY driver can be loaded automatically. This results in a simpler code. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>		2016-01-07 17:47:12 +01:00
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Kconfig	mx6: remove SYS_SOC from board Kconfig	2015-09-13 10:37:29 +02:00
MAINTAINERS	mx6sabresd: Add mx6sabresd_spl_defconfig to MAINTAINERS entry	2014-11-20 10:30:20 +01:00
Makefile	board: arm: convert makefiles to Kbuild style	2013-11-01 11:42:12 -04:00
mx6dlsabresd.cfg	mx6dlsabresd: Use its own DCD table	2014-09-09 16:55:22 +02:00
mx6q_4x_mt41j128.cfg	imx: ddr: Move mx6q_4x_mt41j128.cfg to mx6sabresd board	2014-09-22 16:09:56 +02:00
mx6sabresd.c	mx6sabresd: Simplify the Ethernet PHY configuration	2016-01-07 17:47:12 +01:00