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Svyatoslav Ryhel e63ab85dba ARM: tegra30: clock: implement PLLD2 support 
PLLD2 is a simple clock (controlled by 2 registers) and appears starting
from T30. Primary use of PLLD2 is as main HDMI clock parent.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-12-19 21:24:11 +02:00
..
asm ARM: tegra30: clock: implement PLLD2 support 2023-12-19 21:24:11 +02:00
debug SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00