mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 22:03:15 +00:00
afb4828ede
Add header to handle bootinfo support, needed for Octeon Linux kernel booting. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
350 lines
11 KiB
C
350 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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/*
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* Header file containing the ABI with the bootloader.
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*/
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#ifndef __CVMX_BOOTINFO_H__
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#define __CVMX_BOOTINFO_H__
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#include "cvmx-coremask.h"
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/*
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* Current major and minor versions of the CVMX bootinfo block that is
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* passed from the bootloader to the application. This is versioned
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* so that applications can properly handle multiple bootloader
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* versions.
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*/
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#define CVMX_BOOTINFO_MAJ_VER 1
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#define CVMX_BOOTINFO_MIN_VER 4
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#if (CVMX_BOOTINFO_MAJ_VER == 1)
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#define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20
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/*
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* This structure is populated by the bootloader. For binary
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* compatibility the only changes that should be made are
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* adding members to the end of the structure, and the minor
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* version should be incremented at that time.
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* If an incompatible change is made, the major version
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* must be incremented, and the minor version should be reset
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* to 0.
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*/
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struct cvmx_bootinfo {
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u32 major_version;
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u32 minor_version;
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u64 stack_top;
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u64 heap_base;
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u64 heap_end;
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u64 desc_vaddr;
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u32 exception_base_addr;
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u32 stack_size;
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u32 flags;
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u32 core_mask;
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/* DRAM size in megabytes */
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u32 dram_size;
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/* physical address of free memory descriptor block*/
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u32 phy_mem_desc_addr;
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/* used to pass flags from app to debugger */
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u32 debugger_flags_base_addr;
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/* CPU clock speed, in hz */
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u32 eclock_hz;
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/* DRAM clock speed, in hz */
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u32 dclock_hz;
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u32 reserved0;
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u16 board_type;
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u8 board_rev_major;
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u8 board_rev_minor;
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u16 reserved1;
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u8 reserved2;
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u8 reserved3;
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char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN];
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u8 mac_addr_base[6];
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u8 mac_addr_count;
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#if (CVMX_BOOTINFO_MIN_VER >= 1)
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/*
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* Several boards support compact flash on the Octeon boot
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* bus. The CF memory spaces may be mapped to different
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* addresses on different boards. These are the physical
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* addresses, so care must be taken to use the correct
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* XKPHYS/KSEG0 addressing depending on the application's
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* ABI. These values will be 0 if CF is not present.
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*/
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u64 compact_flash_common_base_addr;
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u64 compact_flash_attribute_base_addr;
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/*
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* Base address of the LED display (as on EBT3000 board)
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* This will be 0 if LED display not present.
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*/
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u64 led_display_base_addr;
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#endif
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#if (CVMX_BOOTINFO_MIN_VER >= 2)
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/* DFA reference clock in hz (if applicable)*/
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u32 dfa_ref_clock_hz;
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/*
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* flags indicating various configuration options. These
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* flags supercede the 'flags' variable and should be used
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* instead if available.
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*/
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u32 config_flags;
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#endif
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#if (CVMX_BOOTINFO_MIN_VER >= 3)
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/*
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* Address of the OF Flattened Device Tree structure
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* describing the board.
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*/
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u64 fdt_addr;
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#endif
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#if (CVMX_BOOTINFO_MIN_VER >= 4)
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/*
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* Coremask used for processors with more than 32 cores
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* or with OCI. This replaces core_mask.
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*/
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struct cvmx_coremask ext_core_mask;
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#endif
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};
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#define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST (1ull << 0)
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#define CVMX_BOOTINFO_CFG_FLAG_PCI_TARGET (1ull << 1)
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#define CVMX_BOOTINFO_CFG_FLAG_DEBUG (1ull << 2)
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#define CVMX_BOOTINFO_CFG_FLAG_NO_MAGIC (1ull << 3)
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/*
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* This flag is set if the TLB mappings are not contained in the
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* 0x10000000 - 0x20000000 boot bus region.
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*/
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#define CVMX_BOOTINFO_CFG_FLAG_OVERSIZE_TLB_MAPPING (1ull << 4)
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#define CVMX_BOOTINFO_CFG_FLAG_BREAK (1ull << 5)
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#endif /* (CVMX_BOOTINFO_MAJ_VER == 1) */
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/* Type defines for board and chip types */
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enum cvmx_board_types_enum {
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CVMX_BOARD_TYPE_NULL = 0,
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CVMX_BOARD_TYPE_SIM = 1,
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CVMX_BOARD_TYPE_EBT3000 = 2,
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CVMX_BOARD_TYPE_KODAMA = 3,
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CVMX_BOARD_TYPE_NIAGARA = 4,
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CVMX_BOARD_TYPE_NAC38 = 5, /* formerly NAO38 */
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CVMX_BOARD_TYPE_THUNDER = 6,
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CVMX_BOARD_TYPE_TRANTOR = 7,
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CVMX_BOARD_TYPE_EBH3000 = 8,
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CVMX_BOARD_TYPE_EBH3100 = 9,
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CVMX_BOARD_TYPE_HIKARI = 10,
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CVMX_BOARD_TYPE_CN3010_EVB_HS5 = 11,
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CVMX_BOARD_TYPE_CN3005_EVB_HS5 = 12,
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CVMX_BOARD_TYPE_KBP = 13,
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/* Deprecated, CVMX_BOARD_TYPE_CN3010_EVB_HS5 supports the CN3020 */
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CVMX_BOARD_TYPE_CN3020_EVB_HS5 = 14,
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CVMX_BOARD_TYPE_EBT5800 = 15,
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CVMX_BOARD_TYPE_NICPRO2 = 16,
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CVMX_BOARD_TYPE_EBH5600 = 17,
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CVMX_BOARD_TYPE_EBH5601 = 18,
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CVMX_BOARD_TYPE_EBH5200 = 19,
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CVMX_BOARD_TYPE_BBGW_REF = 20,
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CVMX_BOARD_TYPE_NIC_XLE_4G = 21,
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CVMX_BOARD_TYPE_EBT5600 = 22,
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CVMX_BOARD_TYPE_EBH5201 = 23,
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CVMX_BOARD_TYPE_EBT5200 = 24,
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CVMX_BOARD_TYPE_CB5600 = 25,
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CVMX_BOARD_TYPE_CB5601 = 26,
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CVMX_BOARD_TYPE_CB5200 = 27,
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/* Special 'generic' board type, supports many boards */
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CVMX_BOARD_TYPE_GENERIC = 28,
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CVMX_BOARD_TYPE_EBH5610 = 29,
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CVMX_BOARD_TYPE_LANAI2_A = 30,
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CVMX_BOARD_TYPE_LANAI2_U = 31,
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CVMX_BOARD_TYPE_EBB5600 = 32,
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CVMX_BOARD_TYPE_EBB6300 = 33,
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CVMX_BOARD_TYPE_NIC_XLE_10G = 34,
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CVMX_BOARD_TYPE_LANAI2_G = 35,
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CVMX_BOARD_TYPE_EBT5810 = 36,
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CVMX_BOARD_TYPE_NIC10E = 37,
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CVMX_BOARD_TYPE_EP6300C = 38,
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CVMX_BOARD_TYPE_EBB6800 = 39,
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CVMX_BOARD_TYPE_NIC4E = 40,
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CVMX_BOARD_TYPE_NIC2E = 41,
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CVMX_BOARD_TYPE_EBB6600 = 42,
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CVMX_BOARD_TYPE_REDWING = 43,
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CVMX_BOARD_TYPE_NIC68_4 = 44,
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CVMX_BOARD_TYPE_NIC10E_66 = 45,
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CVMX_BOARD_TYPE_MAX,
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/*
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* The range from CVMX_BOARD_TYPE_MAX to
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* CVMX_BOARD_TYPE_CUST_DEFINED_MIN is reserved for future
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* SDK use.
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*/
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/*
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* Set aside a range for customer boards. These numbers are managed
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* by Cavium.
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*/
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CVMX_BOARD_TYPE_CUST_DEFINED_MIN = 10000,
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CVMX_BOARD_TYPE_CUST_WSX16 = 10001,
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CVMX_BOARD_TYPE_CUST_NS0216 = 10002,
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CVMX_BOARD_TYPE_CUST_NB5 = 10003,
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CVMX_BOARD_TYPE_CUST_WMR500 = 10004,
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CVMX_BOARD_TYPE_CUST_ITB101 = 10005,
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CVMX_BOARD_TYPE_CUST_NTE102 = 10006,
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CVMX_BOARD_TYPE_CUST_AGS103 = 10007,
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CVMX_BOARD_TYPE_CUST_GST104 = 10008,
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CVMX_BOARD_TYPE_CUST_GCT105 = 10009,
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CVMX_BOARD_TYPE_CUST_AGS106 = 10010,
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CVMX_BOARD_TYPE_CUST_SGM107 = 10011,
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CVMX_BOARD_TYPE_CUST_GCT108 = 10012,
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CVMX_BOARD_TYPE_CUST_AGS109 = 10013,
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CVMX_BOARD_TYPE_CUST_GCT110 = 10014,
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CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER = 10015,
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CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER = 10016,
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CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX = 10017,
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CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX = 10018,
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CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX = 10019,
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CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX = 10020,
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CVMX_BOARD_TYPE_CUST_L2_ZINWELL = 10021,
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CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000,
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/*
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* Set aside a range for customer private use. The SDK won't
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* use any numbers in this range.
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*/
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CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
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CVMX_BOARD_TYPE_UBNT_E100 = 20002,
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CVMX_BOARD_TYPE_CUST_DSR1000N = 20006,
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CVMX_BOARD_TYPE_KONTRON_S1901 = 21901,
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CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,
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/* The remaining range is reserved for future use. */
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};
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enum cvmx_chip_types_enum {
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CVMX_CHIP_TYPE_NULL = 0,
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CVMX_CHIP_SIM_TYPE_DEPRECATED = 1,
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CVMX_CHIP_TYPE_OCTEON_SAMPLE = 2,
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CVMX_CHIP_TYPE_MAX,
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};
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/*
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* Compatibility alias for NAC38 name change, planned to be removed
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* from SDK 1.7
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*/
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#define CVMX_BOARD_TYPE_NAO38 CVMX_BOARD_TYPE_NAC38
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/* Functions to return string based on type */
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#define ENUM_BRD_TYPE_CASE(x) \
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case x: \
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return(#x + 16) /* Skip CVMX_BOARD_TYPE_ */
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static inline const char *cvmx_board_type_to_string(enum
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cvmx_board_types_enum type)
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{
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switch (type) {
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NULL);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_SIM);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT3000);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KODAMA);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIAGARA);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NAC38);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_THUNDER);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_TRANTOR);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3000);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3100);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_HIKARI);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3010_EVB_HS5);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3005_EVB_HS5);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KBP);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3020_EVB_HS5);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5800);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NICPRO2);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5600);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5601);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5200);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_BBGW_REF);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5200);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5600);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5601);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5610);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_A);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_U);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB5600);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6300);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_10G);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_G);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5810);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EP6300C);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6800);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC4E);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC2E);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6600);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_REDWING);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC68_4);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E_66);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX);
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/* Customer boards listed here */
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MIN);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WSX16);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_ITB101);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NTE102);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS103);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GST104);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT105);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS106);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_SGM107);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT108);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS109);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT110);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ZINWELL);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX);
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/* Customer private range */
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DSR1000N);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KONTRON_S1901);
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ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX);
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}
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return NULL;
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}
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#define ENUM_CHIP_TYPE_CASE(x) \
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case x: \
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return(#x + 15) /* Skip CVMX_CHIP_TYPE */
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static inline const char *cvmx_chip_type_to_string(enum
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cvmx_chip_types_enum type)
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{
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switch (type) {
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ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL);
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ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED);
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ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE);
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ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX);
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}
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return "Unsupported Chip";
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}
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#endif /* __CVMX_BOOTINFO_H__ */
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