u-boot/arch/mips/mach-octeon/cache.c
Stefan Roese 399b867fac mips: octeon: cache.c: Flush all pending writes in flush_dcache_range()
As noticed while working on the USB xHCI support, Octeon needs to flush
all pending writes so that the values are present in the memory. Add
this "syncw" instruction (twice) to flush_dcache_range().

Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00

24 lines
481 B
C

// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020 Marvell International Ltd.
*/
#include <cpu_func.h>
/* Octeon memory write barrier */
#define CVMX_SYNCW asm volatile ("syncw\nsyncw\n" : : : "memory")
void flush_dcache_range(ulong start_addr, ulong stop)
{
/* Flush all pending writes */
CVMX_SYNCW;
}
void flush_cache(ulong start_addr, ulong size)
{
}
void invalidate_dcache_range(ulong start_addr, ulong stop)
{
/* Don't need to do anything for OCTEON */
}