mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 01:38:22 +00:00
4fa4267d82
Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
34 lines
917 B
Text
34 lines
917 B
Text
#
|
|
# Cache controllers
|
|
#
|
|
|
|
menu "Cache Controller drivers"
|
|
|
|
config CACHE
|
|
bool "Enable Driver Model for Cache controllers"
|
|
depends on DM
|
|
help
|
|
Enable driver model for cache controllers that are found on
|
|
most CPU's. Cache is memory that the CPU can access directly and
|
|
is usually located on the same chip. This uclass can be used for
|
|
configuring settings that be found from a device tree file.
|
|
|
|
config L2X0_CACHE
|
|
tristate "PL310 cache driver"
|
|
select CACHE
|
|
depends on ARM
|
|
help
|
|
This driver is for the PL310 cache controller commonly found on
|
|
ARMv7(32-bit) devices. The driver configures the cache settings
|
|
found in the device tree.
|
|
|
|
config V5L2_CACHE
|
|
bool "Andes V5L2 cache driver"
|
|
select CACHE
|
|
depends on RISCV_NDS_CACHE
|
|
help
|
|
Support Andes V5L2 cache controller in AE350 platform.
|
|
It will configure tag and data ram timing control from the
|
|
device tree and enable L2 cache.
|
|
|
|
endmenu
|