u-boot/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
Prabhakar Kushwaha 35fe948e3b powerpc/mpc85xx: Add BSC9132/BSC9232 processor support
The BSC9132 is a highly integrated device that targets the evolving
 Microcell, Picocell, and Enterprise-Femto base station market subsegments.

 The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
 core technologies with MAPLE-B2P baseband acceleration processing elements
 to address the need for a high performance, low cost, integrated solution
 that handles all required processing layers without the need for an
 external device except for an RF transceiver or, in a Micro base station
 configuration, a host device that handles the L3/L4 and handover between
 sectors.

 The BSC9132 SoC includes the following function and features:
    - Power Architecture subsystem including two e500 processors with
	512-Kbyte shared L2 cache
    - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
	cache
    - 32 Kbyte of shared M3 memory
    - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
      Processing (MAPLE-B2P)
    - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
      ECC), up to 1333 MHz data rate
    - Dedicated security engine featuring trusted boot
    - Two DMA controllers
         - OCNDMA with four bidirectional channels
         - SysDMA with sixteen bidirectional channels
    - Interfaces
        - Four-lane SerDes PHY
	    - PCI Express controller complies with the PEX Specification-Rev 2.0
        - Two Common Public Radio Interface (CPRI) controller lanes
	    - High-speed USB 2.0 host and device controller with ULPI interface
        - Enhanced secure digital (SD/MMC) host controller (eSDHC)
	    - Antenna interface controller (AIC), supporting four industry
		standard JESD207/four custom ADI RF interfaces
       - ADI lanes support both full duplex FDD support & half duplex TDD
       - Universal Subscriber Identity Module (USIM) interface that
	   facilitates communication to SIM cards or Eurochip pre-paid phone
	   cards
       - Two DUART, two eSPI, and two I2C controllers
       - Integrated Flash memory controller (IFC)
       - GPIO
     - Sixteen 32-bit timers

Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:14 -06:00

96 lines
3.3 KiB
C

/*
* Copyright 2013 Freescale Semiconductor, Inc.
* Author: Prabhakar Kushwaha <prabhakar@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
#define SRDS1_MAX_LANES 4
static u32 serdes1_prtcl_map;
static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
[0] = {NONE, NONE, NONE, NONE},
[1] = {PCIE1, PCIE2, CPRI2, CPRI1},
[2] = {PCIE1, PCIE2, CPRI2, CPRI1},
[3] = {PCIE1, PCIE2, CPRI2, CPRI1},
[4] = {PCIE1, PCIE2, CPRI2, CPRI1},
[5] = {PCIE1, PCIE2, CPRI2, CPRI1},
[6] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
[7] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
[8] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
[9] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
[10] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
[11] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
[12] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
[13] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
[14] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
[15] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
[16] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
[17] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
[18] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
[19] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
[20] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
[21] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
[22] = {PCIE1, PCIE2, CPRI2, CPRI1},
[23] = {PCIE1, PCIE2, CPRI2, CPRI1},
[24] = {PCIE1, PCIE2, CPRI2, CPRI1},
[25] = {PCIE1, PCIE2, CPRI2, CPRI1},
[26] = {PCIE1, PCIE2, CPRI2, CPRI1},
[27] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
[28] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
[29] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
[30] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
[31] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
[32] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
[33] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
[34] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
[35] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
[36] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
[37] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
[38] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
[39] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
[40] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
[41] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
[42] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
[43] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
[44] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
[45] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
[46] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
[47] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
};
int is_serdes_configured(enum srds_prtcl prtcl)
{
return (1 << prtcl) & serdes1_prtcl_map;
}
void fsl_serdes_init(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
}