mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 02:38:56 +00:00
a97ee92e4a
The AM64x SoC uses a central Device Management and Security Controller (DMSC) processor that manages all the low-level device controls including the system-wide SoC reset. The system-wide reset is managed through the system reset driver. Add a sysreset controller node as a child of the dmsc node to enable the "reset" command from U-Boot prompt for the K3 AM642 EVM. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
103 lines
1.5 KiB
Text
103 lines
1.5 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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tick-timer = &timer1;
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};
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};
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&cbass_main{
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u-boot,dm-spl;
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timer1: timer@2400000 {
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compatible = "ti,omap5430-timer";
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reg = <0x0 0x2400000 0x0 0x80>;
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ti,timer-alwon;
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clock-frequency = <250000000>;
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u-boot,dm-spl;
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};
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};
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&main_conf {
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u-boot,dm-spl;
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chipid@14 {
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u-boot,dm-spl;
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};
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};
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&main_pmx0 {
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u-boot,dm-spl;
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main_i2c0_pins_default: main-i2c0-pins-default {
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u-boot,dm-spl;
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
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AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
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>;
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};
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};
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&main_i2c0 {
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u-boot,dm-spl;
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c0_pins_default>;
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clock-frequency = <400000>;
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};
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&main_uart0 {
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u-boot,dm-spl;
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};
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&dmss {
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u-boot,dm-spl;
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};
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&secure_proxy_main {
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u-boot,dm-spl;
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};
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&dmsc {
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u-boot,dm-spl;
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k3_sysreset: sysreset-controller {
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compatible = "ti,sci-sysreset";
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u-boot,dm-spl;
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};
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};
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&k3_pds {
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u-boot,dm-spl;
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};
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&k3_clks {
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u-boot,dm-spl;
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};
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&k3_reset {
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u-boot,dm-spl;
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};
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&sdhci0 {
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u-boot,dm-spl;
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};
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&sdhci1 {
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u-boot,dm-spl;
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};
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&cpsw3g {
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reg = <0x0 0x8000000 0x0 0x200000>,
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<0x0 0x43000200 0x0 0x8>;
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reg-names = "cpsw_nuss", "mac_efuse";
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/delete-property/ ranges;
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cpsw-phy-sel@04044 {
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compatible = "ti,am64-phy-gmii-sel";
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reg = <0x0 0x43004044 0x0 0x8>;
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};
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};
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&cpsw_port2 {
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status = "disabled";
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};
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