mirror of
https://github.com/AsahiLinux/u-boot
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8dcf1df48d
add support for Serial Downloader Boot via UUU as well as flashing emmc via UUU on USB0 Port of phyBOARD Pollux. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
70 lines
1.9 KiB
C
70 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* Copyright (C) 2020 PHYTEC Messtechnik GmbH
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* Author: Teresa Remmet <t.remmet@phytec.de>
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*/
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#ifndef __PHYCORE_IMX8MP_H
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#define __PHYCORE_IMX8MP_H
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#include <linux/sizes.h>
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#include <asm/arch/imx-regs.h>
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#define CFG_SYS_UBOOT_BASE \
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(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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#define CFG_EXTRA_ENV_SETTINGS \
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"image=Image\0" \
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"console=ttymxc0,115200\0" \
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"fdt_addr=0x48000000\0" \
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"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"ip_dyn=yes\0" \
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"dofastboot=0\0" \
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"fastboot_raw_partition_bootloader=64 8128\0" \
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"fastboot_raw_partition_all=0 4194304\0" \
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"emmc_dev=2\0" \
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"sd_dev=1\0" \
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"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
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"mmcpart=1\0" \
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"mmcroot=2\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs console=${console} " \
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"root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
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"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
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"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"if run loadfdt; then " \
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"booti ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi;\0 " \
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"nfsroot=/nfs\0" \
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"netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \
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"nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
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"netboot=echo Booting from net ...; " \
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"run netargs; " \
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"if test ${ip_dyn} = yes; then " \
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"setenv get_cmd dhcp; " \
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"else " \
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"setenv get_cmd tftp; " \
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"fi; " \
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"${get_cmd} ${loadaddr} ${image}; " \
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"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
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"booti ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi;\0" \
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/* Link Definitions */
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#define CFG_SYS_INIT_RAM_ADDR 0x40000000
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#define CFG_SYS_INIT_RAM_SIZE SZ_512K
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#define CFG_SYS_SDRAM_BASE 0x40000000
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#define PHYS_SDRAM 0x40000000
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#define PHYS_SDRAM_SIZE 0x80000000
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#endif /* __PHYCORE_IMX8MP_H */
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