mirror of
https://github.com/AsahiLinux/u-boot
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cd93d625fd
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
176 lines
3.7 KiB
C
176 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2013 Altera Corporation <www.altera.com>
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <reset.h>
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#include <wdt.h>
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#include <asm/io.h>
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#include <asm/utils.h>
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#include <linux/bitops.h>
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#define DW_WDT_CR 0x00
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#define DW_WDT_TORR 0x04
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#define DW_WDT_CRR 0x0C
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#define DW_WDT_CR_EN_OFFSET 0x00
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#define DW_WDT_CR_RMOD_OFFSET 0x01
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#define DW_WDT_CRR_RESTART_VAL 0x76
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struct designware_wdt_priv {
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void __iomem *base;
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unsigned int clk_khz;
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};
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/*
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* Set the watchdog time interval.
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* Counter is 32 bit.
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*/
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static int designware_wdt_settimeout(void __iomem *base, unsigned int clk_khz,
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unsigned int timeout)
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{
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signed int i;
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/* calculate the timeout range value */
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i = log_2_n_round_up(timeout * clk_khz) - 16;
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i = clamp(i, 0, 15);
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writel(i | (i << 4), base + DW_WDT_TORR);
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return 0;
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}
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static void designware_wdt_enable(void __iomem *base)
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{
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writel(BIT(DW_WDT_CR_EN_OFFSET), base + DW_WDT_CR);
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}
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static unsigned int designware_wdt_is_enabled(void __iomem *base)
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{
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return readl(base + DW_WDT_CR) & BIT(0);
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}
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static void designware_wdt_reset_common(void __iomem *base)
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{
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if (designware_wdt_is_enabled(base))
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/* restart the watchdog counter */
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writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR);
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}
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#if !CONFIG_IS_ENABLED(WDT)
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void hw_watchdog_reset(void)
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{
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designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE);
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}
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void hw_watchdog_init(void)
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{
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/* reset to disable the watchdog */
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hw_watchdog_reset();
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/* set timer in miliseconds */
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designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
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CONFIG_DW_WDT_CLOCK_KHZ,
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CONFIG_WATCHDOG_TIMEOUT_MSECS);
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/* enable the watchdog */
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designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE);
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/* reset the watchdog */
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hw_watchdog_reset();
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}
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#else
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static int designware_wdt_reset(struct udevice *dev)
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{
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struct designware_wdt_priv *priv = dev_get_priv(dev);
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designware_wdt_reset_common(priv->base);
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return 0;
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}
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static int designware_wdt_stop(struct udevice *dev)
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{
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struct designware_wdt_priv *priv = dev_get_priv(dev);
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designware_wdt_reset(dev);
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writel(0, priv->base + DW_WDT_CR);
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return 0;
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}
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static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
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{
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struct designware_wdt_priv *priv = dev_get_priv(dev);
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designware_wdt_stop(dev);
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/* set timer in miliseconds */
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designware_wdt_settimeout(priv->base, priv->clk_khz, timeout);
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designware_wdt_enable(priv->base);
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/* reset the watchdog */
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return designware_wdt_reset(dev);
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}
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static int designware_wdt_probe(struct udevice *dev)
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{
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struct designware_wdt_priv *priv = dev_get_priv(dev);
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__maybe_unused int ret;
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priv->base = dev_remap_addr(dev);
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if (!priv->base)
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return -EINVAL;
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#if CONFIG_IS_ENABLED(CLK)
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struct clk clk;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return ret;
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priv->clk_khz = clk_get_rate(&clk);
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if (!priv->clk_khz)
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return -EINVAL;
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#else
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priv->clk_khz = CONFIG_DW_WDT_CLOCK_KHZ;
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#endif
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#if CONFIG_IS_ENABLED(DM_RESET)
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struct reset_ctl_bulk resets;
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ret = reset_get_bulk(dev, &resets);
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if (ret)
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return ret;
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ret = reset_deassert_bulk(&resets);
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if (ret)
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return ret;
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#endif
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/* reset to disable the watchdog */
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return designware_wdt_stop(dev);
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}
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static const struct wdt_ops designware_wdt_ops = {
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.start = designware_wdt_start,
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.reset = designware_wdt_reset,
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.stop = designware_wdt_stop,
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};
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static const struct udevice_id designware_wdt_ids[] = {
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{ .compatible = "snps,dw-wdt"},
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{}
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};
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U_BOOT_DRIVER(designware_wdt) = {
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.name = "designware_wdt",
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.id = UCLASS_WDT,
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.of_match = designware_wdt_ids,
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.priv_auto_alloc_size = sizeof(struct designware_wdt_priv),
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.probe = designware_wdt_probe,
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.ops = &designware_wdt_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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#endif
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