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241 lines
6 KiB
C
241 lines
6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2012 The Chromium OS Authors.
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*/
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/*
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* This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed
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* through the PCI bus. Each PCI device has 256 bytes of configuration space,
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* consisting of a standard header and a device-specific set of registers. PCI
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* bus 0, device 31, function 0 gives us access to the chipset GPIOs (among
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* other things). Within the PCI configuration space, the GPIOBASE register
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* tells us where in the device's I/O region we can find more registers to
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* actually access the GPIOs.
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*
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* PCI bus/device/function 0:1f:0 => PCI config registers
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* PCI config register "GPIOBASE"
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* PCI I/O space + [GPIOBASE] => start of GPIO registers
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* GPIO registers => gpio pin function, direction, value
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*
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*
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* Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most
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* ICH versions have more, but the decoding the matrix that describes them is
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* absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2,
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* but they will ONLY work for certain unspecified chipsets because the offset
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* from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or
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* reserved or subject to arcane restrictions.
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <log.h>
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#include <pch.h>
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#include <pci.h>
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#include <asm/cpu.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define GPIO_PER_BANK 32
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struct ich6_bank_priv {
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/* These are I/O addresses */
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uint16_t use_sel;
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uint16_t io_sel;
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uint16_t lvl;
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u32 lvl_write_cache;
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bool use_lvl_write_cache;
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};
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#define GPIO_USESEL_OFFSET(x) (x)
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#define GPIO_IOSEL_OFFSET(x) (x + 4)
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#define GPIO_LVL_OFFSET(x) (x + 8)
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static int _ich6_gpio_set_value(struct ich6_bank_priv *bank, unsigned offset,
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int value)
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{
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u32 val;
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if (bank->use_lvl_write_cache)
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val = bank->lvl_write_cache;
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else
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val = inl(bank->lvl);
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if (value)
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val |= (1UL << offset);
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else
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val &= ~(1UL << offset);
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outl(val, bank->lvl);
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if (bank->use_lvl_write_cache)
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bank->lvl_write_cache = val;
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return 0;
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}
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static int _ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir)
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{
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u32 val;
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if (!dir) {
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val = inl(base);
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val |= (1UL << offset);
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outl(val, base);
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} else {
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val = inl(base);
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val &= ~(1UL << offset);
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outl(val, base);
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}
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return 0;
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}
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static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
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{
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struct ich6_bank_platdata *plat = dev_get_platdata(dev);
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u32 gpiobase;
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int offset;
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int ret;
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ret = pch_get_gpio_base(dev->parent, &gpiobase);
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if (ret)
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return ret;
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offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
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if (offset == -1) {
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debug("%s: Invalid register offset %d\n", __func__, offset);
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return -EINVAL;
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}
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plat->offset = offset;
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plat->base_addr = gpiobase + offset;
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plat->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
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"bank-name", NULL);
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return 0;
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}
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static int ich6_gpio_probe(struct udevice *dev)
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{
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struct ich6_bank_platdata *plat = dev_get_platdata(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct ich6_bank_priv *bank = dev_get_priv(dev);
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const void *prop;
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uc_priv->gpio_count = GPIO_PER_BANK;
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uc_priv->bank_name = plat->bank_name;
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bank->use_sel = plat->base_addr;
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bank->io_sel = plat->base_addr + 4;
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bank->lvl = plat->base_addr + 8;
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prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
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"use-lvl-write-cache", NULL);
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if (prop)
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bank->use_lvl_write_cache = true;
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else
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bank->use_lvl_write_cache = false;
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bank->lvl_write_cache = 0;
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return 0;
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}
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static int ich6_gpio_request(struct udevice *dev, unsigned offset,
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const char *label)
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{
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struct ich6_bank_priv *bank = dev_get_priv(dev);
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u32 tmplong;
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/*
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* Make sure that the GPIO pin we want isn't already in use for some
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* built-in hardware function. We have to check this for every
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* requested pin.
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*/
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tmplong = inl(bank->use_sel);
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if (!(tmplong & (1UL << offset))) {
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debug("%s: gpio %d is reserved for internal use\n", __func__,
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offset);
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return -EPERM;
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}
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return 0;
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}
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static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset)
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{
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struct ich6_bank_priv *bank = dev_get_priv(dev);
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return _ich6_gpio_set_direction(bank->io_sel, offset, 0);
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}
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static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset,
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int value)
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{
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int ret;
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struct ich6_bank_priv *bank = dev_get_priv(dev);
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ret = _ich6_gpio_set_direction(bank->io_sel, offset, 1);
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if (ret)
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return ret;
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return _ich6_gpio_set_value(bank, offset, value);
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}
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static int ich6_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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struct ich6_bank_priv *bank = dev_get_priv(dev);
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u32 tmplong;
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int r;
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tmplong = inl(bank->lvl);
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if (bank->use_lvl_write_cache)
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tmplong |= bank->lvl_write_cache;
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r = (tmplong & (1UL << offset)) ? 1 : 0;
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return r;
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}
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static int ich6_gpio_set_value(struct udevice *dev, unsigned offset,
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int value)
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{
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struct ich6_bank_priv *bank = dev_get_priv(dev);
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return _ich6_gpio_set_value(bank, offset, value);
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}
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static int ich6_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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struct ich6_bank_priv *bank = dev_get_priv(dev);
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u32 mask = 1UL << offset;
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if (!(inl(bank->use_sel) & mask))
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return GPIOF_FUNC;
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if (inl(bank->io_sel) & mask)
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return GPIOF_INPUT;
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else
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return GPIOF_OUTPUT;
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}
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static const struct dm_gpio_ops gpio_ich6_ops = {
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.request = ich6_gpio_request,
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.direction_input = ich6_gpio_direction_input,
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.direction_output = ich6_gpio_direction_output,
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.get_value = ich6_gpio_get_value,
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.set_value = ich6_gpio_set_value,
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.get_function = ich6_gpio_get_function,
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};
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static const struct udevice_id intel_ich6_gpio_ids[] = {
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{ .compatible = "intel,ich6-gpio" },
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{ }
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};
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U_BOOT_DRIVER(gpio_ich6) = {
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.name = "gpio_ich6",
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.id = UCLASS_GPIO,
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.of_match = intel_ich6_gpio_ids,
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.ops = &gpio_ich6_ops,
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.ofdata_to_platdata = gpio_ich6_ofdata_to_platdata,
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.probe = ich6_gpio_probe,
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.priv_auto_alloc_size = sizeof(struct ich6_bank_priv),
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.platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata),
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};
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