Pragnesh Patel 1ba43d29eb clk: sifive: fu540-prci: Release ethernet clock reset ... U-Boot ethernet works with FSBL flow where releasing ethernet clock reset is part of FSBL itself but with the SPL, We need to release ethernet clock reset explicitly for U-Boot proper. With this change Release ethernet clock reset code in FSBL might not be needed or unaffected. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>		2020-06-04 09:44:09 +08:00
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fu540-prci.c	clk: sifive: fu540-prci: Release ethernet clock reset	2020-06-04 09:44:09 +08:00
Kconfig	clk: sifive: Drop GEMGXL clock driver	2019-07-19 14:24:51 +08:00
Makefile	clk: sifive: Drop GEMGXL clock driver	2019-07-19 14:24:51 +08:00