mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-30 15:03:18 +00:00
78ce0bd3ac
CCF clocks should always use the struct clock passed to their methods for extracting the driver-specific clock information struct. Previously, many functions would use the clk->dev->priv if the device was bound. This could cause problems with composite clocks. The individual clocks in a composite clock did not have the ->dev field filled in. This was fine, because the device-specific clock information would be used. However, since there was no ->dev, there was no way to get the parent clock. This caused the recalc_rate method of the CCF divider clock to fail. One option would be to use the clk->priv field to get the composite clock and from there get the appropriate parent device. However, this would tie the implementation to the composite clock. In general, different devices should not rely on the contents of ->priv from another device. The simple solution to this problem is to just always use the supplied struct clock. The composite clock now fills in the ->dev pointer of its child clocks. This allows child clocks to make calls like clk_get_parent() without issue. imx avoided the above problem by using a custom get_rate function with composite clocks. Signed-off-by: Sean Anderson <seanga2@gmail.com> Acked-by: Lukasz Majewski <lukma@denx.de>
160 lines
3.4 KiB
C
160 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
|
|
* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
|
|
* Copyright 2019 NXP
|
|
*
|
|
* Gated clock implementation
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/io.h>
|
|
#include <malloc.h>
|
|
#include <clk-uclass.h>
|
|
#include <dm/device.h>
|
|
#include <dm/devres.h>
|
|
#include <linux/bitops.h>
|
|
#include <linux/clk-provider.h>
|
|
#include <clk.h>
|
|
#include "clk.h"
|
|
#include <linux/err.h>
|
|
|
|
#define UBOOT_DM_CLK_GATE "clk_gate"
|
|
|
|
/**
|
|
* DOC: basic gatable clock which can gate and ungate it's output
|
|
*
|
|
* Traits of this clock:
|
|
* prepare - clk_(un)prepare only ensures parent is (un)prepared
|
|
* enable - clk_enable and clk_disable are functional & control gating
|
|
* rate - inherits rate from parent. No clk_set_rate support
|
|
* parent - fixed parent. No clk_set_parent support
|
|
*/
|
|
|
|
/*
|
|
* It works on following logic:
|
|
*
|
|
* For enabling clock, enable = 1
|
|
* set2dis = 1 -> clear bit -> set = 0
|
|
* set2dis = 0 -> set bit -> set = 1
|
|
*
|
|
* For disabling clock, enable = 0
|
|
* set2dis = 1 -> set bit -> set = 1
|
|
* set2dis = 0 -> clear bit -> set = 0
|
|
*
|
|
* So, result is always: enable xor set2dis.
|
|
*/
|
|
static void clk_gate_endisable(struct clk *clk, int enable)
|
|
{
|
|
struct clk_gate *gate = to_clk_gate(clk);
|
|
int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
|
|
u32 reg;
|
|
|
|
set ^= enable;
|
|
|
|
if (gate->flags & CLK_GATE_HIWORD_MASK) {
|
|
reg = BIT(gate->bit_idx + 16);
|
|
if (set)
|
|
reg |= BIT(gate->bit_idx);
|
|
} else {
|
|
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
|
|
reg = gate->io_gate_val;
|
|
#else
|
|
reg = readl(gate->reg);
|
|
#endif
|
|
|
|
if (set)
|
|
reg |= BIT(gate->bit_idx);
|
|
else
|
|
reg &= ~BIT(gate->bit_idx);
|
|
}
|
|
|
|
writel(reg, gate->reg);
|
|
}
|
|
|
|
static int clk_gate_enable(struct clk *clk)
|
|
{
|
|
clk_gate_endisable(clk, 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int clk_gate_disable(struct clk *clk)
|
|
{
|
|
clk_gate_endisable(clk, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int clk_gate_is_enabled(struct clk *clk)
|
|
{
|
|
struct clk_gate *gate = to_clk_gate(clk);
|
|
u32 reg;
|
|
|
|
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
|
|
reg = gate->io_gate_val;
|
|
#else
|
|
reg = readl(gate->reg);
|
|
#endif
|
|
|
|
/* if a set bit disables this clk, flip it before masking */
|
|
if (gate->flags & CLK_GATE_SET_TO_DISABLE)
|
|
reg ^= BIT(gate->bit_idx);
|
|
|
|
reg &= BIT(gate->bit_idx);
|
|
|
|
return reg ? 1 : 0;
|
|
}
|
|
|
|
const struct clk_ops clk_gate_ops = {
|
|
.enable = clk_gate_enable,
|
|
.disable = clk_gate_disable,
|
|
.get_rate = clk_generic_get_rate,
|
|
};
|
|
|
|
struct clk *clk_register_gate(struct device *dev, const char *name,
|
|
const char *parent_name, unsigned long flags,
|
|
void __iomem *reg, u8 bit_idx,
|
|
u8 clk_gate_flags, spinlock_t *lock)
|
|
{
|
|
struct clk_gate *gate;
|
|
struct clk *clk;
|
|
int ret;
|
|
|
|
if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
|
|
if (bit_idx > 15) {
|
|
pr_err("gate bit exceeds LOWORD field\n");
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
}
|
|
|
|
/* allocate the gate */
|
|
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
|
if (!gate)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
/* struct clk_gate assignments */
|
|
gate->reg = reg;
|
|
gate->bit_idx = bit_idx;
|
|
gate->flags = clk_gate_flags;
|
|
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
|
|
gate->io_gate_val = *(u32 *)reg;
|
|
#endif
|
|
|
|
clk = &gate->clk;
|
|
|
|
ret = clk_register(clk, UBOOT_DM_CLK_GATE, name, parent_name);
|
|
if (ret) {
|
|
kfree(gate);
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
return clk;
|
|
}
|
|
|
|
U_BOOT_DRIVER(clk_gate) = {
|
|
.name = UBOOT_DM_CLK_GATE,
|
|
.id = UCLASS_CLK,
|
|
.ops = &clk_gate_ops,
|
|
.flags = DM_FLAG_PRE_RELOC,
|
|
};
|