mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-04 10:30:32 +00:00
87a5d60103
* 'master' of git://git.denx.de/u-boot-arm: ARM: Add Calxeda Highbank platform dkb: make mmc command as default enabled Marvell: dkb: add mmc support ARM: pantheon: add mmc definition davinci: remove config.mk file from the sources ARM:AM33XX: Add support for TI AM335X EVM ARM:AM33XX: Added timer support ARM:AM33XX: Add emif/ddr support ARM:AM33XX: Add clock definitions ARM:AM33XX: Added support for AM33xx omap3/emif4: fix registers definition davinci: remove obsolete macro CONFIG_EMAC_MDIO_PHY_NUM davinci: emac: add support for more than 1 PHYs davinci: emac: add new features to autonegotiate for EMAC da850evm: Move LPSC configuration to board_early_init_f() omap4_panda: Build in cmd_gpio support on panda omap: Don't use gpio_free to change direction to input mmc: omap: Allow OMAP_HSMMC[23]_BASE to be unset OMAP3: overo : Add environment variable optargs to bootargs OMAP3: overo: Move ethernet CS4 configuration to execute based on board id OMAP3: overo : Use ttyO2 instead of ttyS2. da830: add support for NAND boot mode dm36x: revert cache disable patch dm644X: revert cache disable patch devkit8000: Add malloc space omap: spl: fix build break due to changes in FAT OMAP3 SPL: Provide weak omap_rev_string omap: beagle: Use ubifs instead of jffs2 for nand boot omap: overo: Disable pull-ups on camera PCLK, HS and VS signals omap: overo: Configure mux for gpio10 SPL: Add DMA library omap3: Add interface for omap3 DMA omap3: Add DMA register accessors omap3: Add Base register for DMA arm, davinci: add missing LSPC define for MMC/SD1 U-Boot/SPL: omap4: Make ddr pre-calculated timings as default. DaVinci: correct MDSTAT.STATE mask omap4: splitting padconfs into common, 4430 and 4460 omap4: adding revision detection for 4460 ES1.1 omap4: replacing OMAP4_CONTROL with OMAP4430_CONTROL gplug: fixed build error as a result of code cleanup patch kirkwood_spi: add dummy spi_init() gpio: mvmfp: reduce include platform file ARM: orion5x: reduce dependence of including platform file serial: reduce include platform file for marvell chip ARM: kirkwood: reduce dependence of including platform file ARM: armada100: reduce dependence of including platform file ARM: pantheon: reduce dependence of including platform file Armada100: Add env storage support for Marvell gplugD Armada100: Add SPI flash support for Marvell gplugD Armada100: Add SPI support for Marvell gplugD SPI: Add SPI driver support for Marvell Armada100 dreamplug: initial board support. imx: fix coding style misc: pmic: drop old Freescale's pmic driver MX31: mx31pdk: use new pmic driver MX31: mx31ads: use new pmic driver MX31: mx31_litekit: use new pmic driver MX5: mx53evk: use new pmic driver MX5: mx51evk: use new pmic driver MX35: mx35pdk: use new pmic driver misc: pmic: addI2C support to pmic_fsl driver misc: pmic: use I2C_SET_BUS in pmic I2C MX5: efikamx/efikasb: use new pmic driver MX3: qong: use new pmic driver RTC: Switch mc13783 to generic pmic code MX5: vision2: use new pmic driver misc: pmic: Freescale PMIC switches to generic PMIC driver misc:pmic:samsung Enable PMIC driver at GONI target misc:pmic:max8998 MAX8998 support at a new PMIC driver. misc:pmic:core New generic PMIC driver mx31pdk: Remove unneeded config mx31: provide readable WEIM CS accessor MX51: vision2: Set global macros I2C: Add i2c_get/set_speed() to mxc_i2c.c ARM: Update mach-types devkit8000: Add config to enable SPL MMC boot devkit8000: protect board_mmc_init arm, post: add missing post_time_ms for arm cosmetic, post: Codingstyle cleanup arm, logbuffer: make it compileclean tegra2: Enable MMC for Seaboard tegra2: Add more pinmux functions tegra2: Rename PIN_ to PINGRP_ tegra2: Add more clock functions tegra2: Clean up board code a little tegra2: Rename CLOCK_PLL_ID to CLOCK_ID
190 lines
4.5 KiB
C
190 lines
4.5 KiB
C
/*
|
|
* (C) Copyright 2009
|
|
* Marvell Semiconductor <www.marvell.com>
|
|
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
|
*
|
|
* Derived from drivers/spi/mpc8xxx_spi.c
|
|
*
|
|
* See file CREDITS for list of people who contributed to this
|
|
* project.
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
|
* MA 02110-1301 USA
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <malloc.h>
|
|
#include <spi.h>
|
|
#include <asm/io.h>
|
|
#include <asm/arch/kirkwood.h>
|
|
#include <asm/arch/spi.h>
|
|
#include <asm/arch/mpp.h>
|
|
|
|
static struct kwspi_registers *spireg = (struct kwspi_registers *)KW_SPI_BASE;
|
|
|
|
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
|
|
unsigned int max_hz, unsigned int mode)
|
|
{
|
|
struct spi_slave *slave;
|
|
u32 data;
|
|
u32 kwspi_mpp_config[] = {
|
|
MPP0_GPIO,
|
|
MPP7_SPI_SCn,
|
|
0
|
|
};
|
|
|
|
if (!spi_cs_is_valid(bus, cs))
|
|
return NULL;
|
|
|
|
slave = malloc(sizeof(struct spi_slave));
|
|
if (!slave)
|
|
return NULL;
|
|
|
|
slave->bus = bus;
|
|
slave->cs = cs;
|
|
|
|
writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, &spireg->ctrl);
|
|
|
|
/* calculate spi clock prescaller using max_hz */
|
|
data = ((CONFIG_SYS_TCLK / 2) / max_hz) & KWSPI_CLKPRESCL_MASK;
|
|
data |= 0x10;
|
|
|
|
/* program spi clock prescaller using max_hz */
|
|
writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg);
|
|
debug("data = 0x%08x \n", data);
|
|
|
|
writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
|
|
writel(KWSPI_IRQMASK, spireg->irq_mask);
|
|
|
|
/* program mpp registers to select SPI_CSn */
|
|
if (cs) {
|
|
kwspi_mpp_config[0] = MPP0_GPIO;
|
|
kwspi_mpp_config[1] = MPP7_SPI_SCn;
|
|
} else {
|
|
kwspi_mpp_config[0] = MPP0_SPI_SCn;
|
|
kwspi_mpp_config[1] = MPP7_GPO;
|
|
}
|
|
kirkwood_mpp_conf(kwspi_mpp_config);
|
|
|
|
return slave;
|
|
}
|
|
|
|
void spi_free_slave(struct spi_slave *slave)
|
|
{
|
|
free(slave);
|
|
}
|
|
|
|
int spi_claim_bus(struct spi_slave *slave)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
void spi_release_bus(struct spi_slave *slave)
|
|
{
|
|
}
|
|
|
|
#ifndef CONFIG_SPI_CS_IS_VALID
|
|
/*
|
|
* you can define this function board specific
|
|
* define above CONFIG in board specific config file and
|
|
* provide the function in board specific src file
|
|
*/
|
|
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
|
|
{
|
|
return (bus == 0 && (cs == 0 || cs == 1));
|
|
}
|
|
#endif
|
|
|
|
void spi_init(void)
|
|
{
|
|
}
|
|
|
|
void spi_cs_activate(struct spi_slave *slave)
|
|
{
|
|
writel(readl(&spireg->ctrl) | KWSPI_IRQUNMASK, &spireg->ctrl);
|
|
}
|
|
|
|
void spi_cs_deactivate(struct spi_slave *slave)
|
|
{
|
|
writel(readl(&spireg->ctrl) & KWSPI_IRQMASK, &spireg->ctrl);
|
|
}
|
|
|
|
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
|
|
void *din, unsigned long flags)
|
|
{
|
|
unsigned int tmpdout, tmpdin;
|
|
int tm, isread = 0;
|
|
|
|
debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n",
|
|
slave->bus, slave->cs, dout, din, bitlen);
|
|
|
|
if (flags & SPI_XFER_BEGIN)
|
|
spi_cs_activate(slave);
|
|
|
|
/*
|
|
* handle data in 8-bit chunks
|
|
* TBD: 2byte xfer mode to be enabled
|
|
*/
|
|
writel(((readl(&spireg->cfg) & ~KWSPI_XFERLEN_MASK) |
|
|
KWSPI_XFERLEN_1BYTE), &spireg->cfg);
|
|
|
|
while (bitlen > 4) {
|
|
debug("loopstart bitlen %d\n", bitlen);
|
|
tmpdout = 0;
|
|
|
|
/* Shift data so it's msb-justified */
|
|
if (dout)
|
|
tmpdout = *(u32 *) dout & 0x0ff;
|
|
|
|
writel(~KWSPI_SMEMRDIRQ, &spireg->irq_cause);
|
|
writel(tmpdout, &spireg->dout); /* Write the data out */
|
|
debug("*** spi_xfer: ... %08x written, bitlen %d\n",
|
|
tmpdout, bitlen);
|
|
|
|
/*
|
|
* Wait for SPI transmit to get out
|
|
* or time out (1 second = 1000 ms)
|
|
* The NE event must be read and cleared first
|
|
*/
|
|
for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) {
|
|
if (readl(&spireg->irq_cause) & KWSPI_SMEMRDIRQ) {
|
|
isread = 1;
|
|
tmpdin = readl(&spireg->din);
|
|
debug
|
|
("spi_xfer: din %p..%08x read\n",
|
|
din, tmpdin);
|
|
|
|
if (din) {
|
|
*((u8 *) din) = (u8) tmpdin;
|
|
din += 1;
|
|
}
|
|
if (dout)
|
|
dout += 1;
|
|
bitlen -= 8;
|
|
}
|
|
if (isread)
|
|
break;
|
|
}
|
|
if (tm >= KWSPI_TIMEOUT)
|
|
printf("*** spi_xfer: Time out during SPI transfer\n");
|
|
|
|
debug("loopend bitlen %d\n", bitlen);
|
|
}
|
|
|
|
if (flags & SPI_XFER_END)
|
|
spi_cs_deactivate(slave);
|
|
|
|
return 0;
|
|
}
|