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bb772a5944
Add the emif configurations required for omap5 soc.Add the correct ddr part configurations required for omap5 evm board. EDB8164B3PH from ELPIDA is the part used on the board. Also changes are done to retain some part of the code common for OMAP4/5 and keep only the remaining in the Soc specific directories. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
167 lines
4.7 KiB
C
167 lines
4.7 KiB
C
/*
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*
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* Common functions for OMAP4 based boards
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Aneesh V <aneesh@ti.com>
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* Steve Sakoman <steve@sakoman.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/armv7.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/sizes.h>
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#include <asm/emif.h>
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#include <asm/arch/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
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static const struct gpio_bank gpio_bank_44xx[6] = {
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{ (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
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{ (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
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};
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const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
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#ifdef CONFIG_SPL_BUILD
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/*
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* Some tuning of IOs for optimal power and performance
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*/
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void do_io_settings(void)
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{
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u32 lpddr2io;
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struct control_lpddr2io_regs *lpddr2io_regs =
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(struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
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struct omap4_sys_ctrl_regs *const ctrl =
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(struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
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u32 omap4_rev = omap_revision();
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if (omap4_rev == OMAP4430_ES1_0)
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lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
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else if (omap4_rev == OMAP4430_ES2_0)
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lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
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else
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lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
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/* EMIF1 */
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writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
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writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
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/* No pull for GR10 as per hw team's recommendation */
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writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
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&lpddr2io_regs->control_lpddr2io1_2);
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writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3);
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/* EMIF2 */
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writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
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writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
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/* No pull for GR10 as per hw team's recommendation */
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writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
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&lpddr2io_regs->control_lpddr2io2_2);
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writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3);
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/*
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* Some of these settings (TRIM values) come from eFuse and are
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* in turn programmed in the eFuse at manufacturing time after
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* calibration of the device. Do the software over-ride only if
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* the device is not correctly trimmed
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*/
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if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) {
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writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
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&ctrl->control_ldosram_iva_voltage_ctrl);
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writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
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&ctrl->control_ldosram_mpu_voltage_ctrl);
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writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
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&ctrl->control_ldosram_core_voltage_ctrl);
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}
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if (!readl(&ctrl->control_efuse_1))
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writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
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if (!readl(&ctrl->control_efuse_2))
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writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
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}
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#endif
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void init_omap_revision(void)
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{
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/*
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* For some of the ES2/ES1 boards ID_CODE is not reliable:
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* Also, ES1 and ES2 have different ARM revisions
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* So use ARM revision for identification
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*/
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unsigned int arm_rev = cortex_rev();
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switch (arm_rev) {
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case MIDR_CORTEX_A9_R0P1:
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*omap4_revision = OMAP4430_ES1_0;
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break;
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case MIDR_CORTEX_A9_R1P2:
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switch (readl(CONTROL_ID_CODE)) {
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case OMAP4_CONTROL_ID_CODE_ES2_0:
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*omap4_revision = OMAP4430_ES2_0;
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break;
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case OMAP4_CONTROL_ID_CODE_ES2_1:
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*omap4_revision = OMAP4430_ES2_1;
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break;
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case OMAP4_CONTROL_ID_CODE_ES2_2:
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*omap4_revision = OMAP4430_ES2_2;
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break;
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default:
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*omap4_revision = OMAP4430_ES2_0;
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break;
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}
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break;
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case MIDR_CORTEX_A9_R1P3:
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*omap4_revision = OMAP4430_ES2_3;
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break;
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case MIDR_CORTEX_A9_R2P10:
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*omap4_revision = OMAP4460_ES1_0;
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break;
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default:
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*omap4_revision = OMAP4430_SILICON_ID_INVALID;
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break;
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}
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}
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#ifndef CONFIG_SYS_L2CACHE_OFF
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void v7_outer_cache_enable(void)
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{
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set_pl310_ctrl_reg(1);
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}
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void v7_outer_cache_disable(void)
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{
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set_pl310_ctrl_reg(0);
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}
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#endif
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