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55bdc200ad
Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
181 lines
4.1 KiB
C
181 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2020-2021 Texas Instruments Incorporated - http://www.ti.com
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* Tero Kristo <t-kristo@ti.com>
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*/
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#ifndef __K3_CLK_H__
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#define __K3_CLK_H__
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <linux/clk-provider.h>
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#include <linux/types.h>
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#include <stdint.h>
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struct dev_clk {
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int dev_id;
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int clk_id;
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const char *clk_name;
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};
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#define DEV_CLK(_dev_id, _clk_id, _clk_name) { .dev_id = _dev_id, \
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.clk_id = _clk_id, .clk_name = _clk_name, }
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#define CLK_TYPE_MUX 0x01
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#define CLK_TYPE_DIV 0x02
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#define CLK_TYPE_PLL 0x03
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#define CLK_TYPE_HFOSC 0x04
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#define CLK_TYPE_POSTDIV 0x05
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#define CLK_TYPE_MUX_PLLCTRL 0x06
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#define CLK_TYPE_FIXED_RATE 0x07
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struct pll_data {
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u32 reg;
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const char *name;
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const char *parent;
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u32 flags;
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};
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struct mux_data {
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u32 reg;
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const char *name;
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const char * const *parents;
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int num_parents;
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u32 flags;
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int shift;
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int width;
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};
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struct div_data {
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u32 reg;
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const char *name;
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const char *parent;
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u32 flags;
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int shift;
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int width;
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u32 div_flags;
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};
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struct hfosc_data {
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const char *name;
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u32 flags;
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};
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struct fixed_rate_data {
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const char *name;
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u64 rate;
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u32 flags;
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};
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struct postdiv_data {
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const char *name;
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const char *parent;
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int width;
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u32 flags;
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};
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struct mux_pllctrl_data {
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u32 reg;
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const char *name;
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const char * const *parents;
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int num_parents;
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u32 flags;
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};
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struct clk_data {
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int type;
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u32 default_freq;
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union {
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struct pll_data pll;
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struct mux_data mux;
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struct div_data div;
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struct hfosc_data hfosc;
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struct postdiv_data postdiv;
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struct mux_pllctrl_data mux_pllctrl;
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struct fixed_rate_data fixed_rate;
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} clk;
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};
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#define CLK_MUX(_name, _parents, _num_parents, _reg, _shift, _width, _flags) \
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{ \
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.type = CLK_TYPE_MUX, \
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.clk.mux = { .name = _name, .parents = _parents, \
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.reg = _reg, \
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.num_parents = _num_parents, .shift = _shift, \
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.width = _width, .flags = _flags } \
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}
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#define CLK_DIV(_name, _parent, _reg, _shift, _width, _flags, _div_flags) \
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{ \
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.type = CLK_TYPE_DIV, \
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.clk.div = { \
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.name = _name, .parent = _parent, .reg = _reg, \
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.shift = _shift, .width = _width, \
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.flags = _flags, .div_flags = _div_flags } \
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}
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#define CLK_DIV_DEFFREQ(_name, _parent, _reg, _shift, _width, _flags, _div_flags, _freq) \
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{ \
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.type = CLK_TYPE_DIV, \
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.default_freq = _freq, \
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.clk.div = { \
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.name = _name, .parent = _parent, .reg = _reg, \
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.shift = _shift, .width = _width, \
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.flags = _flags, .div_flags = _div_flags } \
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}
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#define CLK_PLL(_name, _parent, _reg, _flags) \
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{ \
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.type = CLK_TYPE_PLL, \
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.clk.pll = {.name = _name, .parent = _parent, .reg = _reg, .flags = _flags } \
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}
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#define CLK_PLL_DEFFREQ(_name, _parent, _reg, _flags, _freq) \
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{ \
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.type = CLK_TYPE_PLL, \
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.default_freq = _freq, \
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.clk.pll = { .name = _name, .parent = _parent, \
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.reg = _reg, .flags = _flags } \
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}
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#define CLK_HFOSC(_name, _flags) \
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{ \
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.type = CLK_TYPE_HFOSC, \
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.clk.hfosc = { .name = _name, .flags = _flags } \
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}
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#define CLK_FIXED_RATE(_name, _rate, _flags) \
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{ \
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.type = CLK_TYPE_FIXED_RATE, \
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.clk.fixed_rate = { .name = _name, .rate = _rate, .flags = _flags } \
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}
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#define CLK_POSTDIV(_name, _parent, _width, _flags) \
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{ \
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.type = CLK_TYPE_POSTDIV, \
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.clk.postdiv = {.name = _name, .parent = _parent, .width = _width, .flags = _flags } \
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}
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#define CLK_MUX_PLLCTRL(_name, _parents, _num_parents, _reg, _flags) \
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{ \
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.type = CLK_TYPE_MUX, \
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.clk.mux_pllctrl = { .name = _name, .parents = _parents,\
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.num_parents = _num_parents, .flags = _flags } \
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}
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struct ti_k3_clk_platdata {
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const struct clk_data *clk_list;
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int clk_list_cnt;
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const struct dev_clk *soc_dev_clk_data;
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int soc_dev_clk_data_cnt;
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};
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extern const struct ti_k3_clk_platdata j721e_clk_platdata;
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extern const struct ti_k3_clk_platdata j7200_clk_platdata;
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extern const struct ti_k3_clk_platdata j721s2_clk_platdata;
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struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
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void __iomem *reg);
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#endif /* __K3_CLK_H__ */
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