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bb907ab51f
This patch adds a board_reset function to allow boards to specify their own custom reset sequence (e.g. resetting by timing out watchdog). Tested only on MCF5271, can be expanded if needed. Based on Mike Frysinger's suggestion on: http://article.gmane.org/gmane.comp.boot-loaders.u-boot/70304 Signed-off-by: Richard Retanubun <RichardRetanubun at RuggedCom.com>
408 lines
9 KiB
C
408 lines
9 KiB
C
/*
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* (C) Copyright 2003
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* Josef Baumgartner <josef.baumgartner@telex.de>
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*
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* MCF5282 additionals
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* (C) Copyright 2005
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* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
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*
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* MCF5275 additions
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* Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <asm/immap.h>
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#include <netdev.h>
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#include "cpu.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_M5208
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int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
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{
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volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
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udelay(1000);
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rcm->rcr = RCM_RCR_SOFTRST;
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/* we don't return! */
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return 0;
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};
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int checkcpu(void)
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{
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char buf1[32], buf2[32];
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printf("CPU: Freescale Coldfire MCF5208\n"
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" CPU CLK %s MHz BUS CLK %s MHz\n",
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strmhz(buf1, gd->cpu_clk),
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strmhz(buf2, gd->bus_clk));
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return 0;
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};
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#if defined(CONFIG_WATCHDOG)
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/* Called by macro WATCHDOG_RESET */
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void watchdog_reset(void)
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{
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volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
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wdt->sr = 0x5555;
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wdt->sr = 0xAAAA;
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}
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int watchdog_disable(void)
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{
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volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
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wdt->sr = 0x5555; /* reset watchdog counteDECLARE_GLOBAL_DATA_PTR;
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r */
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wdt->sr = 0xAAAA;
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wdt->cr = 0; /* disable watchdog timer */
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puts("WATCHDOG:disabled\n");
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return (0);
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}
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int watchdog_init(void)
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{
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volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
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wdt->cr = 0; /* disable watchdog */
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/* set timeout and enable watchdog */
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wdt->mr =
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((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
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wdt->sr = 0x5555; /* reset watchdog counter */
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wdt->sr = 0xAAAA;
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puts("WATCHDOG:enabled\n");
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return (0);
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}
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#endif /* #ifdef CONFIG_WATCHDOG */
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#endif /* #ifdef CONFIG_M5208 */
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#ifdef CONFIG_M5271
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/*
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* Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
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* determine which one we are running on, based on the Chip Identification
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* Register (CIR).
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*/
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int checkcpu(void)
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{
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char buf[32];
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unsigned short cir; /* Chip Identification Register */
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unsigned short pin; /* Part identification number */
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unsigned char prn; /* Part revision number */
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char *cpu_model;
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cir = mbar_readShort(MCF_CCM_CIR);
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pin = cir >> MCF_CCM_CIR_PIN_LEN;
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prn = cir & MCF_CCM_CIR_PRN_MASK;
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switch (pin) {
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case MCF_CCM_CIR_PIN_MCF5270:
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cpu_model = "5270";
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break;
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case MCF_CCM_CIR_PIN_MCF5271:
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cpu_model = "5271";
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break;
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default:
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cpu_model = NULL;
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break;
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}
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if (cpu_model)
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printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
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cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
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else
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printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
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" (PIN: 0x%x) rev. %hu, at %s MHz\n",
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pin, prn, strmhz(buf, CONFIG_SYS_CLK));
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return 0;
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}
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int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
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{
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/* Call the board specific reset actions first. */
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if(board_reset) {
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board_reset();
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}
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mbar_writeByte(MCF_RCM_RCR,
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MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
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return 0;
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};
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#if defined(CONFIG_WATCHDOG)
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void watchdog_reset(void)
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{
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mbar_writeShort(MCF_WTM_WSR, 0x5555);
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mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
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}
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int watchdog_disable(void)
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{
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mbar_writeShort(MCF_WTM_WCR, 0);
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return (0);
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}
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int watchdog_init(void)
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{
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mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
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return (0);
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}
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#endif /* #ifdef CONFIG_WATCHDOG */
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#endif
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#ifdef CONFIG_M5272
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int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
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{
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volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
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wdp->wdog_wrrr = 0;
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udelay(1000);
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/* enable watchdog, set timeout to 0 and wait */
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wdp->wdog_wrrr = 1;
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while (1) ;
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/* we don't return! */
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return 0;
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};
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int checkcpu(void)
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{
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volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
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uchar msk;
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char *suf;
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puts("CPU: ");
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msk = (sysctrl->sc_dir > 28) & 0xf;
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switch (msk) {
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case 0x2:
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suf = "1K75N";
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break;
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case 0x4:
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suf = "3K75N";
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break;
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default:
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suf = NULL;
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printf("Freescale MCF5272 (Mask:%01x)\n", msk);
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break;
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}
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if (suf)
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printf("Freescale MCF5272 %s\n", suf);
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return 0;
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};
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#if defined(CONFIG_WATCHDOG)
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/* Called by macro WATCHDOG_RESET */
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void watchdog_reset(void)
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{
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volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
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wdt->wdog_wcr = 0;
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}
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int watchdog_disable(void)
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{
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volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
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wdt->wdog_wcr = 0; /* reset watchdog counter */
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wdt->wdog_wirr = 0; /* disable watchdog interrupt */
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wdt->wdog_wrrr = 0; /* disable watchdog timer */
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puts("WATCHDOG:disabled\n");
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return (0);
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}
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int watchdog_init(void)
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{
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volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
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wdt->wdog_wirr = 0; /* disable watchdog interrupt */
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/* set timeout and enable watchdog */
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wdt->wdog_wrrr =
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((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
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wdt->wdog_wcr = 0; /* reset watchdog counter */
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puts("WATCHDOG:enabled\n");
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return (0);
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}
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#endif /* #ifdef CONFIG_WATCHDOG */
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#endif /* #ifdef CONFIG_M5272 */
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#ifdef CONFIG_M5275
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int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
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{
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volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
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udelay(1000);
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rcm->rcr = RCM_RCR_SOFTRST;
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/* we don't return! */
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return 0;
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};
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int checkcpu(void)
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{
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char buf[32];
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printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
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strmhz(buf, CONFIG_SYS_CLK));
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return 0;
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};
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#if defined(CONFIG_WATCHDOG)
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/* Called by macro WATCHDOG_RESET */
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void watchdog_reset(void)
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{
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volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
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wdt->wsr = 0x5555;
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wdt->wsr = 0xAAAA;
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}
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int watchdog_disable(void)
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{
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volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
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wdt->wsr = 0x5555; /* reset watchdog counter */
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wdt->wsr = 0xAAAA;
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wdt->wcr = 0; /* disable watchdog timer */
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puts("WATCHDOG:disabled\n");
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return (0);
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}
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int watchdog_init(void)
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{
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volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
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wdt->wcr = 0; /* disable watchdog */
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/* set timeout and enable watchdog */
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wdt->wmr =
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((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
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wdt->wsr = 0x5555; /* reset watchdog counter */
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wdt->wsr = 0xAAAA;
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puts("WATCHDOG:enabled\n");
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return (0);
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}
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#endif /* #ifdef CONFIG_WATCHDOG */
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#endif /* #ifdef CONFIG_M5275 */
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#ifdef CONFIG_M5282
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int checkcpu(void)
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{
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unsigned char resetsource = MCFRESET_RSR;
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printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
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MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
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printf("Reset:%s%s%s%s%s%s%s\n",
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(resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
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(resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
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(resetsource & MCFRESET_RSR_EXT) ? " External" : "",
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(resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
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(resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
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(resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
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(resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
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return 0;
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}
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int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
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{
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MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
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return 0;
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};
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#endif
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#ifdef CONFIG_M5249
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int checkcpu(void)
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{
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char buf[32];
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printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
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strmhz(buf, CONFIG_SYS_CLK));
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return 0;
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}
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int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
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{
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/* enable watchdog, set timeout to 0 and wait */
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mbar_writeByte(MCFSIM_SYPCR, 0xc0);
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while (1) ;
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/* we don't return! */
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return 0;
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};
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#endif
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#ifdef CONFIG_M5253
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int checkcpu(void)
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{
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char buf[32];
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unsigned char resetsource = mbar_readLong(SIM_RSR);
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printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
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strmhz(buf, CONFIG_SYS_CLK));
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if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
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printf("Reset:%s%s\n",
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(resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
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: "",
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(resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
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"");
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}
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return 0;
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}
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int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
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{
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/* enable watchdog, set timeout to 0 and wait */
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mbar_writeByte(SIM_SYPCR, 0xc0);
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while (1) ;
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/* we don't return! */
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return 0;
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};
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#endif
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#if defined(CONFIG_MCFFEC)
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/* Default initializations for MCFFEC controllers. To override,
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* create a board-specific function called:
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* int board_eth_init(bd_t *bis)
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*/
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int cpu_eth_init(bd_t *bis)
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{
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return mcffec_initialize(bis);
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}
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#endif
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