mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-25 20:43:32 +00:00
d4143373f1
Perform a simple rename of CONFIG_X86_REFCODE_ADDR to CFG_X86_REFCODE_ADDR Signed-off-by: Tom Rini <trini@konsulko.com>
181 lines
3 KiB
Text
181 lines
3 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2016 Google, Inc
|
|
* Written by Simon Glass <sjg@chromium.org>
|
|
*/
|
|
|
|
#include <config.h>
|
|
|
|
/ {
|
|
binman {
|
|
multiple-images;
|
|
rom: rom {
|
|
};
|
|
};
|
|
};
|
|
|
|
#ifdef CONFIG_ROM_SIZE
|
|
&rom {
|
|
filename = "u-boot.rom";
|
|
end-at-4gb;
|
|
sort-by-offset;
|
|
pad-byte = <0xff>;
|
|
size = <CONFIG_ROM_SIZE>;
|
|
#ifdef CONFIG_HAVE_INTEL_ME
|
|
intel-descriptor {
|
|
filename = CONFIG_FLASH_DESCRIPTOR_FILE;
|
|
};
|
|
intel-me {
|
|
filename = CONFIG_INTEL_ME_FILE;
|
|
};
|
|
#endif
|
|
#ifdef CONFIG_TPL
|
|
#ifdef CONFIG_HAVE_MICROCODE
|
|
u-boot-tpl-with-ucode-ptr {
|
|
offset = <CONFIG_TPL_TEXT_BASE>;
|
|
};
|
|
u-boot-tpl-dtb {
|
|
};
|
|
#endif
|
|
u-boot-spl {
|
|
type = "u-boot-spl";
|
|
offset = <CONFIG_X86_OFFSET_SPL>;
|
|
};
|
|
u-boot {
|
|
offset = <CONFIG_X86_OFFSET_U_BOOT>;
|
|
};
|
|
#elif defined(CONFIG_SPL)
|
|
u-boot-spl-with-ucode-ptr {
|
|
offset = <CONFIG_X86_OFFSET_SPL>;
|
|
};
|
|
u-boot-dtb-with-ucode2 {
|
|
type = "u-boot-dtb-with-ucode";
|
|
};
|
|
u-boot {
|
|
offset = <CONFIG_X86_OFFSET_U_BOOT>;
|
|
};
|
|
#else
|
|
# ifdef CONFIG_HAVE_MICROCODE
|
|
/* If there is no SPL then we need to put microcode in U-Boot */
|
|
u-boot-with-ucode-ptr {
|
|
offset = <CONFIG_X86_OFFSET_U_BOOT>;
|
|
};
|
|
# else
|
|
u-boot-nodtb {
|
|
offset = <CONFIG_X86_OFFSET_U_BOOT>;
|
|
};
|
|
# endif
|
|
#endif
|
|
#ifdef CONFIG_HAVE_MICROCODE
|
|
u-boot-dtb-with-ucode {
|
|
};
|
|
u-boot-ucode {
|
|
align = <16>;
|
|
};
|
|
#else
|
|
u-boot-dtb {
|
|
};
|
|
#endif
|
|
fdtmap {
|
|
};
|
|
#ifdef CONFIG_HAVE_X86_FIT
|
|
intel-fit {
|
|
};
|
|
intel-fit-ptr {
|
|
};
|
|
#endif
|
|
#ifdef CONFIG_HAVE_MRC
|
|
intel-mrc {
|
|
offset = <CFG_X86_MRC_ADDR>;
|
|
};
|
|
#endif
|
|
#ifdef CONFIG_FSP_VERSION1
|
|
intel-fsp {
|
|
filename = CONFIG_FSP_FILE;
|
|
offset = <CONFIG_FSP_ADDR>;
|
|
};
|
|
#endif
|
|
#ifdef CONFIG_FSP_VERSION2
|
|
intel-descriptor {
|
|
filename = CONFIG_FLASH_DESCRIPTOR_FILE;
|
|
};
|
|
intel-ifwi {
|
|
filename = CONFIG_IFWI_INPUT_FILE;
|
|
convert-fit;
|
|
|
|
section {
|
|
size = <0x8000>;
|
|
ifwi-replace;
|
|
ifwi-subpart = "IBBP";
|
|
ifwi-entry = "IBBL";
|
|
u-boot-tpl {
|
|
};
|
|
x86-start16-tpl {
|
|
offset = <0x7800>;
|
|
};
|
|
x86-reset16-tpl {
|
|
offset = <0x7ff0>;
|
|
};
|
|
};
|
|
};
|
|
intel-fsp-m {
|
|
filename = CONFIG_FSP_FILE_M;
|
|
};
|
|
intel-fsp-s {
|
|
filename = CONFIG_FSP_FILE_S;
|
|
};
|
|
#endif
|
|
private_files: private-files {
|
|
type = "files";
|
|
pattern = "*.dat";
|
|
};
|
|
#ifdef CONFIG_HAVE_CMC
|
|
intel-cmc {
|
|
filename = CONFIG_CMC_FILE;
|
|
offset = <CONFIG_CMC_ADDR>;
|
|
};
|
|
#endif
|
|
#ifdef CONFIG_HAVE_VGA_BIOS
|
|
intel-vga {
|
|
filename = CONFIG_VGA_BIOS_FILE;
|
|
offset = <CONFIG_VGA_BIOS_ADDR>;
|
|
};
|
|
#endif
|
|
#ifdef CONFIG_HAVE_VBT
|
|
intel-vbt {
|
|
filename = CONFIG_VBT_FILE;
|
|
offset = <CONFIG_VBT_ADDR>;
|
|
};
|
|
#endif
|
|
#ifdef CONFIG_HAVE_REFCODE
|
|
intel-refcode {
|
|
offset = <CFG_X86_REFCODE_ADDR>;
|
|
};
|
|
#endif
|
|
#ifdef CONFIG_TPL
|
|
x86-start16-tpl {
|
|
offset = <CONFIG_SYS_X86_START16>;
|
|
};
|
|
x86-reset16-tpl {
|
|
offset = <CONFIG_RESET_VEC_LOC>;
|
|
};
|
|
#elif defined(CONFIG_SPL)
|
|
x86-start16-spl {
|
|
offset = <CONFIG_SYS_X86_START16>;
|
|
};
|
|
x86-reset16-spl {
|
|
offset = <CONFIG_RESET_VEC_LOC>;
|
|
};
|
|
#else
|
|
x86-start16 {
|
|
offset = <CONFIG_SYS_X86_START16>;
|
|
};
|
|
x86-reset16 {
|
|
offset = <CONFIG_RESET_VEC_LOC>;
|
|
};
|
|
#endif
|
|
image-header {
|
|
location = "end";
|
|
};
|
|
};
|
|
#endif
|