u-boot/board/xes/common/fsl_8xxx_clk.c
Tom Rini e4c3ce7e28 CONFIG_SYS_CLK_FREQ: Consistently be static or get_board_sys_clk()
This CONFIG option is used in one of two ways.  The first way is that it
is defined to a static value, of an unsigned long size.  The second way
is that it is defined to something, typically a function, to determine
this value at run time.

However, in a few cases that function returns a static value.  Change
that to using the static value directly.

In the case of using something at run time, convert everything to using
a function of the same name and prototype.  This will allow for further
cleanups.

Finally, we have a few cases where the function is just not used, so
drop it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00

53 lines
1.1 KiB
C

// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*/
#include <common.h>
#include <asm/io.h>
/*
* Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
*/
unsigned long get_board_sys_clk(void)
{
#if defined(CONFIG_MPC85xx)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#elif defined(CONFIG_MPC86xx)
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
#endif
if (in_be32(&gur->gpporcr) & 0x10000)
return 66666666;
else
#ifdef CONFIG_ARCH_P2020
return 100000000;
#else
return 50000000;
#endif
}
#ifdef CONFIG_MPC85xx
/*
* Return DDR input clock - synchronous with SYSCLK or 66 MHz
* Note: 86xx doesn't support asynchronous DDR clk
*/
unsigned long get_board_ddr_clk(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
if (ddr_ratio == 0x7)
return get_board_sys_clk();
#ifdef CONFIG_ARCH_P2020
if (in_be32(&gur->gpporcr) & 0x20000)
return 66666666;
else
return 100000000;
#else
return 66666666;
#endif
}
#endif