mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-27 15:12:21 +00:00
4549e789c1
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have multiple licenses (in these cases, dual license) declared in the SPDX-License-Identifier tag. In this case we change from listing "LICENSE-A LICENSE-B" or "LICENSE-A or LICENSE-B" or "(LICENSE-A OR LICENSE-B)" to "LICENSE-A OR LICENSE-B" as per the Linux Kernel style document. Note that parenthesis are allowed so when they were used before we continue to use them. Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
604 lines
13 KiB
Text
604 lines
13 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
|
/*
|
|
* Copyright (c) 2013 MundoReader S.L.
|
|
* Author: Heiko Stuebner <heiko@sntech.de>
|
|
*/
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/pinctrl/rockchip.h>
|
|
#include <dt-bindings/clock/rk3188-cru.h>
|
|
#include "rk3xxx.dtsi"
|
|
|
|
/ {
|
|
compatible = "rockchip,rk3188";
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
enable-method = "rockchip,rk3066-smp";
|
|
|
|
cpu0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
next-level-cache = <&L2>;
|
|
reg = <0x0>;
|
|
operating-points = <
|
|
/* kHz uV */
|
|
1608000 1350000
|
|
1416000 1250000
|
|
1200000 1150000
|
|
1008000 1075000
|
|
816000 975000
|
|
600000 950000
|
|
504000 925000
|
|
312000 875000
|
|
>;
|
|
clock-latency = <40000>;
|
|
clocks = <&cru ARMCLK>;
|
|
};
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
next-level-cache = <&L2>;
|
|
reg = <0x1>;
|
|
};
|
|
cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
next-level-cache = <&L2>;
|
|
reg = <0x2>;
|
|
};
|
|
cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
next-level-cache = <&L2>;
|
|
reg = <0x3>;
|
|
};
|
|
};
|
|
|
|
sram: sram@10080000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0x10080000 0x8000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x10080000 0x8000>;
|
|
|
|
smp-sram@0 {
|
|
compatible = "rockchip,rk3066-smp-sram";
|
|
reg = <0x0 0x50>;
|
|
};
|
|
};
|
|
|
|
i2s0: i2s@1011a000 {
|
|
compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
|
|
reg = <0x1011a000 0x2000>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s0_bus>;
|
|
dmas = <&dmac1_s 6>, <&dmac1_s 7>;
|
|
dma-names = "tx", "rx";
|
|
clock-names = "i2s_hclk", "i2s_clk";
|
|
clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
|
|
rockchip,playback-channels = <2>;
|
|
rockchip,capture-channels = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spdif: sound@1011e000 {
|
|
compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
|
|
reg = <0x1011e000 0x2000>;
|
|
#sound-dai-cells = <0>;
|
|
clock-names = "hclk", "mclk";
|
|
clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
|
|
dmas = <&dmac1_s 8>;
|
|
dma-names = "tx";
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spdif_tx>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cru: clock-controller@20000000 {
|
|
compatible = "rockchip,rk3188-cru";
|
|
reg = <0x20000000 0x1000>;
|
|
rockchip,grf = <&grf>;
|
|
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
efuse: efuse@20010000 {
|
|
compatible = "rockchip,rockchip-efuse";
|
|
reg = <0x20010000 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
clocks = <&cru PCLK_EFUSE>;
|
|
clock-names = "pclk_efuse";
|
|
|
|
cpu_leakage: cpu_leakage@17 {
|
|
reg = <0x17 0x1>;
|
|
};
|
|
};
|
|
|
|
timer3: timer@2000e000 {
|
|
compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
|
|
reg = <0x2000e000 0x20>;
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
usbphy: phy {
|
|
compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
|
|
rockchip,grf = <&grf>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
usbphy0: usb-phy@10c {
|
|
#phy-cells = <0>;
|
|
reg = <0x10c>;
|
|
clocks = <&cru SCLK_OTGPHY0>;
|
|
clock-names = "phyclk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
usbphy1: usb-phy@11c {
|
|
#phy-cells = <0>;
|
|
reg = <0x11c>;
|
|
clocks = <&cru SCLK_OTGPHY1>;
|
|
clock-names = "phyclk";
|
|
#clock-cells = <0>;
|
|
};
|
|
};
|
|
|
|
pinctrl: pinctrl {
|
|
compatible = "rockchip,rk3188-pinctrl";
|
|
rockchip,grf = <&grf>;
|
|
rockchip,pmu = <&pmu>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
gpio0: gpio0@2000a000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x2000a000 0x100>;
|
|
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO0>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio1: gpio1@2003c000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x2003c000 0x100>;
|
|
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO1>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio2@2003e000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x2003e000 0x100>;
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO2>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio3@20080000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x20080000 0x100>;
|
|
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO3>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
pcfg_pull_up: pcfg_pull_up {
|
|
bias-pull-up;
|
|
};
|
|
|
|
pcfg_pull_down: pcfg_pull_down {
|
|
bias-pull-down;
|
|
};
|
|
|
|
pcfg_pull_none: pcfg_pull_none {
|
|
bias-disable;
|
|
};
|
|
|
|
emmc {
|
|
emmc_clk: emmc-clk {
|
|
rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
|
|
emmc_cmd: emmc-cmd {
|
|
rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
|
|
emmc_rst: emmc-rst {
|
|
rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
|
|
/*
|
|
* The data pins are shared between nandc and emmc and
|
|
* not accessible through pinctrl. Also they should've
|
|
* been already set correctly by firmware, as
|
|
* flash/emmc is the boot-device.
|
|
*/
|
|
};
|
|
|
|
emac {
|
|
emac_xfer: emac-xfer {
|
|
rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
|
|
<RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
|
|
<RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
|
|
<RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
|
|
<RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
|
|
<RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
|
|
<RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
|
|
<RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
|
|
};
|
|
|
|
emac_mdio: emac-mdio {
|
|
rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
|
|
<RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c0 {
|
|
i2c0_xfer: i2c0-xfer {
|
|
rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c1 {
|
|
i2c1_xfer: i2c1-xfer {
|
|
rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c2 {
|
|
i2c2_xfer: i2c2-xfer {
|
|
rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c3 {
|
|
i2c3_xfer: i2c3-xfer {
|
|
rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
|
|
<RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c4 {
|
|
i2c4_xfer: i2c4-xfer {
|
|
rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm0 {
|
|
pwm0_out: pwm0-out {
|
|
rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm1 {
|
|
pwm1_out: pwm1-out {
|
|
rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm2 {
|
|
pwm2_out: pwm2-out {
|
|
rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm3 {
|
|
pwm3_out: pwm3-out {
|
|
rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spi0 {
|
|
spi0_clk: spi0-clk {
|
|
rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi0_cs0: spi0-cs0 {
|
|
rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi0_tx: spi0-tx {
|
|
rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi0_rx: spi0-rx {
|
|
rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
spi0_cs1: spi0-cs1 {
|
|
rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi1 {
|
|
spi1_clk: spi1-clk {
|
|
rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
spi1_cs0: spi1-cs0 {
|
|
rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
spi1_rx: spi1-rx {
|
|
rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
spi1_tx: spi1-tx {
|
|
rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
|
|
};
|
|
spi1_cs1: spi1-cs1 {
|
|
rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
uart0_xfer: uart0-xfer {
|
|
rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
|
|
<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_cts: uart0-cts {
|
|
rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_rts: uart0-rts {
|
|
rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
uart1_xfer: uart1-xfer {
|
|
rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
|
|
<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart1_cts: uart1-cts {
|
|
rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart1_rts: uart1-rts {
|
|
rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2 {
|
|
uart2_xfer: uart2-xfer {
|
|
rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
|
|
<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
/* no rts / cts for uart2 */
|
|
};
|
|
|
|
uart3 {
|
|
uart3_xfer: uart3-xfer {
|
|
rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
|
|
<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart3_cts: uart3-cts {
|
|
rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart3_rts: uart3-rts {
|
|
rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sd0 {
|
|
sd0_clk: sd0-clk {
|
|
rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd0_cmd: sd0-cmd {
|
|
rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd0_cd: sd0-cd {
|
|
rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd0_wp: sd0-wp {
|
|
rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd0_pwr: sd0-pwr {
|
|
rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd0_bus1: sd0-bus-width1 {
|
|
rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd0_bus4: sd0-bus-width4 {
|
|
rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sd1 {
|
|
sd1_clk: sd1-clk {
|
|
rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd1_cmd: sd1-cmd {
|
|
rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd1_cd: sd1-cd {
|
|
rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd1_wp: sd1-wp {
|
|
rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd1_bus1: sd1-bus-width1 {
|
|
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd1_bus4: sd1-bus-width4 {
|
|
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2s0 {
|
|
i2s0_bus: i2s0-bus {
|
|
rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spdif {
|
|
spdif_tx: spdif-tx {
|
|
rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&emac {
|
|
compatible = "rockchip,rk3188-emac";
|
|
};
|
|
|
|
&global_timer {
|
|
interrupts = <GIC_PPI 11 0xf04>;
|
|
};
|
|
|
|
&grf {
|
|
compatible = "rockchip,rk3188-grf", "syscon";
|
|
};
|
|
|
|
&local_timer {
|
|
interrupts = <GIC_PPI 13 0xf04>;
|
|
};
|
|
|
|
&i2c0 {
|
|
compatible = "rockchip,rk3188-i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_xfer>;
|
|
};
|
|
|
|
&i2c1 {
|
|
compatible = "rockchip,rk3188-i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_xfer>;
|
|
};
|
|
|
|
&i2c2 {
|
|
compatible = "rockchip,rk3188-i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_xfer>;
|
|
};
|
|
|
|
&i2c3 {
|
|
compatible = "rockchip,rk3188-i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3_xfer>;
|
|
};
|
|
|
|
&i2c4 {
|
|
compatible = "rockchip,rk3188-i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c4_xfer>;
|
|
};
|
|
|
|
&pmu {
|
|
compatible = "rockchip,rk3188-pmu", "syscon";
|
|
};
|
|
|
|
&pwm0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm0_out>;
|
|
};
|
|
|
|
&pwm1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm1_out>;
|
|
};
|
|
|
|
&pwm2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm2_out>;
|
|
};
|
|
|
|
&pwm3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm3_out>;
|
|
};
|
|
|
|
&spi0 {
|
|
compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
|
|
};
|
|
|
|
&spi1 {
|
|
compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
|
|
};
|
|
|
|
&uart0 {
|
|
compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart0_xfer>;
|
|
};
|
|
|
|
&uart1 {
|
|
compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart1_xfer>;
|
|
};
|
|
|
|
&uart2 {
|
|
compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart2_xfer>;
|
|
};
|
|
|
|
&uart3 {
|
|
compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart3_xfer>;
|
|
};
|
|
|
|
&wdt {
|
|
compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
|
|
};
|