mirror of
https://github.com/AsahiLinux/u-boot
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e4ad6031a7
Intel Quark SoC integrates two 10/100 ethernet controllers which can be connected to an external RMII PHY. The MAC IP is from Designware. Enable this support with the existing U-Boot Designware MAC driver so that the ethernet port on Intel Galileo board can be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
137 lines
3 KiB
C
137 lines
3 KiB
C
/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mmc.h>
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#include <netdev.h>
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#include <phy.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/post.h>
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#include <asm/processor.h>
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#include <asm/arch/device.h>
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#include <asm/arch/msg_port.h>
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#include <asm/arch/quark.h>
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static struct pci_device_id mmc_supported[] = {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO },
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};
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/*
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* TODO:
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*
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* This whole routine should be removed until we fully convert the ICH SPI
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* driver to DM and make use of DT to pass the bios control register offset
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*/
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static void unprotect_spi_flash(void)
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{
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u32 bc;
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bc = pci_read_config32(QUARK_LEGACY_BRIDGE, 0xd8);
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bc |= 0x1; /* unprotect the flash */
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pci_write_config32(QUARK_LEGACY_BRIDGE, 0xd8, bc);
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}
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static void quark_setup_bars(void)
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{
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/* GPIO - D31:F0:R44h */
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pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA,
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CONFIG_GPIO_BASE | IO_BAR_EN);
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/* ACPI PM1 Block - D31:F0:R48h */
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pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK,
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CONFIG_ACPI_PM1_BASE | IO_BAR_EN);
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/* GPE0 - D31:F0:R4Ch */
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pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK,
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CONFIG_ACPI_GPE0_BASE | IO_BAR_EN);
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/* WDT - D31:F0:R84h */
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pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA,
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CONFIG_WDT_BASE | IO_BAR_EN);
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/* RCBA - D31:F0:RF0h */
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pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA,
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CONFIG_RCBA_BASE | MEM_BAR_EN);
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/* ACPI P Block - Msg Port 04:R70h */
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msg_port_write(MSG_PORT_RMU, PBLK_BA,
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CONFIG_ACPI_PBLK_BASE | IO_BAR_EN);
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/* SPI DMA - Msg Port 04:R7Ah */
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msg_port_write(MSG_PORT_RMU, SPI_DMA_BA,
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CONFIG_SPI_DMA_BASE | IO_BAR_EN);
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/* PCIe ECAM */
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msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL,
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CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
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msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG,
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CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
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}
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int arch_cpu_init(void)
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{
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struct pci_controller *hose;
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int ret;
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post_code(POST_CPU_INIT);
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#ifdef CONFIG_SYS_X86_TSC_TIMER
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timer_set_base(rdtsc());
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#endif
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ret = x86_cpu_init_f();
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if (ret)
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return ret;
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ret = pci_early_init_hose(&hose);
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if (ret)
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return ret;
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/*
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* Quark SoC has some non-standard BARs (excluding PCI standard BARs)
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* which need be initialized with suggested values
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*/
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quark_setup_bars();
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unprotect_spi_flash();
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return 0;
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}
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int print_cpuinfo(void)
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{
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post_code(POST_CPU_INFO);
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return default_print_cpuinfo();
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}
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void reset_cpu(ulong addr)
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{
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/* cold reset */
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outb(0x08, PORT_RESET);
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}
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int cpu_mmc_init(bd_t *bis)
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{
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return pci_mmc_init("Quark SDHCI", mmc_supported,
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ARRAY_SIZE(mmc_supported));
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}
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int cpu_eth_init(bd_t *bis)
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{
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u32 base;
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int ret0, ret1;
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pci_read_config_dword(QUARK_EMAC0, PCI_BASE_ADDRESS_0, &base);
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ret0 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);
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pci_read_config_dword(QUARK_EMAC1, PCI_BASE_ADDRESS_0, &base);
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ret1 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);
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if (ret0 < 0 && ret1 < 0)
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return -1;
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else
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return 0;
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}
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