mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-15 01:17:39 +00:00
661 lines
14 KiB
Text
661 lines
14 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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//
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// Device Tree Source for UniPhier LD11 SoC
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//
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// Copyright (C) 2016 Socionext Inc.
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// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/gpio/uniphier-gpio.h>
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/ {
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compatible = "socionext,uniphier-ld11";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0 0x000>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0 0x001>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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operating-points-v2 = <&cluster0_opp>;
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};
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};
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cluster0_opp: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-245000000 {
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opp-hz = /bits/ 64 <245000000>;
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clock-latency-ns = <300>;
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};
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opp-250000000 {
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opp-hz = /bits/ 64 <250000000>;
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clock-latency-ns = <300>;
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};
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opp-490000000 {
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opp-hz = /bits/ 64 <490000000>;
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clock-latency-ns = <300>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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clock-latency-ns = <300>;
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};
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opp-653334000 {
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opp-hz = /bits/ 64 <653334000>;
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clock-latency-ns = <300>;
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};
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opp-666667000 {
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opp-hz = /bits/ 64 <666667000>;
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clock-latency-ns = <300>;
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};
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opp-980000000 {
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opp-hz = /bits/ 64 <980000000>;
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clock-latency-ns = <300>;
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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clocks {
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refclk: ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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};
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emmc_pwrseq: emmc-pwrseq {
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compatible = "mmc-pwrseq-emmc";
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reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 4>,
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<1 14 4>,
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<1 11 4>,
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<1 10 4>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure-memory@81000000 {
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reg = <0x0 0x81000000 0x0 0x01000000>;
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no-map;
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};
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};
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soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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spi0: spi@54006000 {
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compatible = "socionext,uniphier-scssi";
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status = "disabled";
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reg = <0x54006000 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 39 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi0>;
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clocks = <&peri_clk 11>;
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resets = <&peri_rst 11>;
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};
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spi1: spi@54006100 {
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compatible = "socionext,uniphier-scssi";
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status = "disabled";
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reg = <0x54006100 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 216 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi1>;
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clocks = <&peri_clk 12>;
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resets = <&peri_rst 12>;
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};
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serial0: serial@54006800 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006800 0x40>;
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interrupts = <0 33 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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clocks = <&peri_clk 0>;
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resets = <&peri_rst 0>;
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};
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serial1: serial@54006900 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006900 0x40>;
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interrupts = <0 35 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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clocks = <&peri_clk 1>;
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resets = <&peri_rst 1>;
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};
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serial2: serial@54006a00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006a00 0x40>;
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interrupts = <0 37 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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clocks = <&peri_clk 2>;
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resets = <&peri_rst 2>;
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};
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serial3: serial@54006b00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006b00 0x40>;
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interrupts = <0 177 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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clocks = <&peri_clk 3>;
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resets = <&peri_rst 3>;
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};
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gpio: gpio@55000000 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000000 0x200>;
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interrupt-parent = <&aidet>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 0>,
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<&pinctrl 43 0 0>,
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<&pinctrl 51 0 0>,
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<&pinctrl 96 0 0>,
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<&pinctrl 160 0 0>,
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<&pinctrl 184 0 0>;
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gpio-ranges-group-names = "gpio_range0",
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"gpio_range1",
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"gpio_range2",
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"gpio_range3",
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"gpio_range4",
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"gpio_range5";
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ngpios = <200>;
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socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
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<21 217 3>;
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};
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audio@56000000 {
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compatible = "socionext,uniphier-ld11-aio";
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reg = <0x56000000 0x80000>;
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interrupts = <0 144 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_aout1>,
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<&pinctrl_aoutiec1>;
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clock-names = "aio";
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clocks = <&sys_clk 40>;
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reset-names = "aio";
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resets = <&sys_rst 40>;
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#sound-dai-cells = <1>;
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socionext,syscon = <&soc_glue>;
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i2s_port0: port@0 {
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i2s_hdmi: endpoint {
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};
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};
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i2s_port1: port@1 {
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i2s_pcmin2: endpoint {
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};
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};
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i2s_port2: port@2 {
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i2s_line: endpoint {
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dai-format = "i2s";
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remote-endpoint = <&evea_line>;
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};
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};
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i2s_port3: port@3 {
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i2s_hpcmout1: endpoint {
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};
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};
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i2s_port4: port@4 {
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i2s_hp: endpoint {
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dai-format = "i2s";
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remote-endpoint = <&evea_hp>;
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};
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};
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spdif_port0: port@5 {
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spdif_hiecout1: endpoint {
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};
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};
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src_port0: port@6 {
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i2s_epcmout2: endpoint {
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};
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};
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src_port1: port@7 {
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i2s_epcmout3: endpoint {
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};
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};
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comp_spdif_port0: port@8 {
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comp_spdif_hiecout1: endpoint {
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};
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};
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};
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codec@57900000 {
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compatible = "socionext,uniphier-evea";
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reg = <0x57900000 0x1000>;
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clock-names = "evea", "exiv";
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clocks = <&sys_clk 41>, <&sys_clk 42>;
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reset-names = "evea", "exiv", "adamv";
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resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
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#sound-dai-cells = <1>;
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port@0 {
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evea_line: endpoint {
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remote-endpoint = <&i2s_line>;
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};
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};
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port@1 {
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evea_hp: endpoint {
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remote-endpoint = <&i2s_hp>;
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};
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};
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};
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adamv@57920000 {
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compatible = "socionext,uniphier-ld11-adamv",
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"simple-mfd", "syscon";
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reg = <0x57920000 0x1000>;
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adamv_rst: reset {
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compatible = "socionext,uniphier-ld11-adamv-reset";
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#reset-cells = <1>;
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};
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};
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i2c0: i2c@58780000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58780000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 41 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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clocks = <&peri_clk 4>;
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resets = <&peri_rst 4>;
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clock-frequency = <100000>;
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};
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i2c1: i2c@58781000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58781000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 42 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clocks = <&peri_clk 5>;
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resets = <&peri_rst 5>;
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clock-frequency = <100000>;
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};
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i2c2: i2c@58782000 {
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compatible = "socionext,uniphier-fi2c";
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reg = <0x58782000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 43 4>;
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clocks = <&peri_clk 6>;
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resets = <&peri_rst 6>;
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clock-frequency = <400000>;
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};
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i2c3: i2c@58783000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58783000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 44 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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clocks = <&peri_clk 7>;
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resets = <&peri_rst 7>;
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clock-frequency = <100000>;
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};
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i2c4: i2c@58784000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58784000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 45 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c4>;
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clocks = <&peri_clk 8>;
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resets = <&peri_rst 8>;
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clock-frequency = <100000>;
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};
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i2c5: i2c@58785000 {
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compatible = "socionext,uniphier-fi2c";
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reg = <0x58785000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 25 4>;
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clocks = <&peri_clk 9>;
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resets = <&peri_rst 9>;
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clock-frequency = <400000>;
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};
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system_bus: system-bus@58c00000 {
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compatible = "socionext,uniphier-system-bus";
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status = "disabled";
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reg = <0x58c00000 0x400>;
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#address-cells = <2>;
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#size-cells = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_system_bus>;
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};
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smpctrl@59801000 {
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compatible = "socionext,uniphier-smpctrl";
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reg = <0x59801000 0x400>;
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};
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sdctrl@59810000 {
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compatible = "socionext,uniphier-ld11-sdctrl",
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"simple-mfd", "syscon";
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reg = <0x59810000 0x400>;
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sd_rst: reset {
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compatible = "socionext,uniphier-ld11-sd-reset";
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#reset-cells = <1>;
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};
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};
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perictrl@59820000 {
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compatible = "socionext,uniphier-ld11-perictrl",
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"simple-mfd", "syscon";
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reg = <0x59820000 0x200>;
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peri_clk: clock {
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compatible = "socionext,uniphier-ld11-peri-clock";
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#clock-cells = <1>;
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};
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peri_rst: reset {
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compatible = "socionext,uniphier-ld11-peri-reset";
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#reset-cells = <1>;
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};
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};
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emmc: mmc@5a000000 {
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compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
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reg = <0x5a000000 0x400>;
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interrupts = <0 78 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_emmc>;
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clocks = <&sys_clk 4>;
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resets = <&sys_rst 4>;
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bus-width = <8>;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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mmc-pwrseq = <&emmc_pwrseq>;
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cdns,phy-input-delay-legacy = <9>;
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cdns,phy-input-delay-mmc-highspeed = <2>;
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cdns,phy-input-delay-mmc-ddr = <3>;
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cdns,phy-dll-delay-sdclk = <21>;
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cdns,phy-dll-delay-sdclk-hsmmc = <21>;
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};
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usb0: usb@5a800100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a800100 0x100>;
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interrupts = <0 243 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>;
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clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
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<&mio_clk 12>;
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
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<&mio_rst 12>;
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phy-names = "usb";
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phys = <&usb_phy0>;
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has-transaction-translator;
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};
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usb1: usb@5a810100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a810100 0x100>;
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interrupts = <0 244 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1>;
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clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
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<&mio_clk 13>;
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
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<&mio_rst 13>;
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phy-names = "usb";
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phys = <&usb_phy1>;
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has-transaction-translator;
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};
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usb2: usb@5a820100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a820100 0x100>;
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interrupts = <0 245 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb2>;
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clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
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<&mio_clk 14>;
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
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<&mio_rst 14>;
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phy-names = "usb";
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phys = <&usb_phy2>;
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has-transaction-translator;
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};
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mioctrl@5b3e0000 {
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compatible = "socionext,uniphier-ld11-mioctrl",
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"simple-mfd", "syscon";
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reg = <0x5b3e0000 0x800>;
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mio_clk: clock {
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compatible = "socionext,uniphier-ld11-mio-clock";
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#clock-cells = <1>;
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};
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mio_rst: reset {
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compatible = "socionext,uniphier-ld11-mio-reset";
|
|
#reset-cells = <1>;
|
|
resets = <&sys_rst 7>;
|
|
};
|
|
};
|
|
|
|
soc_glue: soc-glue@5f800000 {
|
|
compatible = "socionext,uniphier-ld11-soc-glue",
|
|
"simple-mfd", "syscon";
|
|
reg = <0x5f800000 0x2000>;
|
|
|
|
pinctrl: pinctrl {
|
|
compatible = "socionext,uniphier-ld11-pinctrl";
|
|
};
|
|
|
|
usb-phy {
|
|
compatible = "socionext,uniphier-ld11-usb2-phy";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
usb_phy0: phy@0 {
|
|
reg = <0>;
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
usb_phy1: phy@1 {
|
|
reg = <1>;
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
usb_phy2: phy@2 {
|
|
reg = <2>;
|
|
#phy-cells = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
soc-glue@5f900000 {
|
|
compatible = "socionext,uniphier-ld11-soc-glue-debug",
|
|
"simple-mfd";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x5f900000 0x2000>;
|
|
|
|
efuse@100 {
|
|
compatible = "socionext,uniphier-efuse";
|
|
reg = <0x100 0x28>;
|
|
};
|
|
|
|
efuse@200 {
|
|
compatible = "socionext,uniphier-efuse";
|
|
reg = <0x200 0x68>;
|
|
};
|
|
};
|
|
|
|
xdmac: dma-controller@5fc10000 {
|
|
compatible = "socionext,uniphier-xdmac";
|
|
reg = <0x5fc10000 0x5300>;
|
|
interrupts = <0 188 4>;
|
|
dma-channels = <16>;
|
|
#dma-cells = <2>;
|
|
};
|
|
|
|
aidet: interrupt-controller@5fc20000 {
|
|
compatible = "socionext,uniphier-ld11-aidet";
|
|
reg = <0x5fc20000 0x200>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gic: interrupt-controller@5fe00000 {
|
|
compatible = "arm,gic-v3";
|
|
reg = <0x5fe00000 0x10000>, /* GICD */
|
|
<0x5fe40000 0x80000>; /* GICR */
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <1 9 4>;
|
|
};
|
|
|
|
sysctrl@61840000 {
|
|
compatible = "socionext,uniphier-ld11-sysctrl",
|
|
"simple-mfd", "syscon";
|
|
reg = <0x61840000 0x10000>;
|
|
|
|
sys_clk: clock {
|
|
compatible = "socionext,uniphier-ld11-clock";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
sys_rst: reset {
|
|
compatible = "socionext,uniphier-ld11-reset";
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
watchdog {
|
|
compatible = "socionext,uniphier-wdt";
|
|
};
|
|
};
|
|
|
|
eth: ethernet@65000000 {
|
|
compatible = "socionext,uniphier-ld11-ave4";
|
|
status = "disabled";
|
|
reg = <0x65000000 0x8500>;
|
|
interrupts = <0 66 4>;
|
|
clock-names = "ether";
|
|
clocks = <&sys_clk 6>;
|
|
reset-names = "ether";
|
|
resets = <&sys_rst 6>;
|
|
phy-mode = "internal";
|
|
local-mac-address = [00 00 00 00 00 00];
|
|
socionext,syscon-phy-mode = <&soc_glue 0>;
|
|
|
|
mdio: mdio {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
nand: nand-controller@68000000 {
|
|
compatible = "socionext,uniphier-denali-nand-v5b";
|
|
status = "disabled";
|
|
reg-names = "nand_data", "denali_reg";
|
|
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
|
|
interrupts = <0 65 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_nand>;
|
|
clock-names = "nand", "nand_x", "ecc";
|
|
clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
|
|
reset-names = "nand", "reg";
|
|
resets = <&sys_rst 2>, <&sys_rst 2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "uniphier-pinctrl.dtsi"
|
|
|
|
&pinctrl_aoutiec1 {
|
|
drive-strength = <4>; /* default: 4mA */
|
|
|
|
ao1arc {
|
|
pins = "AO1ARC";
|
|
drive-strength = <8>; /* 8mA */
|
|
};
|
|
};
|