mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 18:59:44 +00:00
268 lines
8.8 KiB
C
268 lines
8.8 KiB
C
/*
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* (C) Copyright 2003
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* Configuation settings for the IXDP425 board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_IXP425 1 /* This is an IXP425 CPU */
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#define CONFIG_IXDP425 1 /* on an IXDP425 Board */
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#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
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#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
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/*
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* select serial console configuration
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*/
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#define CONFIG_IXP_SERIAL
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#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOARD_EARLY_INIT_F 1
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/***************************************************************
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* U-boot generic defines start here.
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***************************************************************/
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/* Command line configuration. */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ELF
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#define CONFIG_PCI
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#ifdef CONFIG_PCI
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#define CONFIG_CMD_PCI
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#define CONFIG_PCI_PNP
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#define CONFIG_IXP_PCI
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_CMD_PCI_ENUM
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#define CONFIG_EEPRO100
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#endif
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#define CONFIG_BOOTCOMMAND "run boot_flash"
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/* enable passing of ATAGs */
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#define CONFIG_CMDLINE_TAG 1
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
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/* timer clock - 2* OSC_IN system clock */
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#define CONFIG_IXP425_TIMER_CLK 66666666
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#define CONFIG_SYS_HZ 1000
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/* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0x00010000
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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/***************************************************************
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* Platform/Board specific defines start here.
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***************************************************************/
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/*
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* Hardware drivers
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*/
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/*
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* Physical Memory Map
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*/
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#define CONFIG_SYS_TEXT_BASE 0x50000000
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#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */
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#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
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#define PHYS_FLASH_BANK_SIZE 0x00800000 /* 8 MB Banks */
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#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CONFIG_BOARD_SIZE_LIMIT 262144
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/* Expansion bus settings */
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#define CONFIG_SYS_EXP_CS0 0xbcd23c42
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/* SDRAM settings */
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */
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#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDR_CONFIG 0xd
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#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
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#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
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/*
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
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#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000)
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#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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/* Use common CFI driver */
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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/* no byte writes on IXP4xx */
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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/* print 'E' for empty sector on flinfo */
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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/* Ethernet */
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/* include IXP4xx NPE support */
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#define CONFIG_IXP4XX_NPE 1
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#define CONFIG_NET_MULTI 1
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/* NPE0 PHY address */
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#define CONFIG_PHY_ADDR 0
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/* NPE1 PHY address (HW Release E only) */
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#define CONFIG_PHY1_ADDR 1
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/* MII PHY management */
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#define CONFIG_MII 1
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/* Number of ethernet rx buffers & descriptors */
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#define CONFIG_SYS_RX_ETH_BUFFER 16
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#define CONFIG_HAS_ETH1 1
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#undef CONFIG_CMD_NFS
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/* Cache Configuration */
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"npe_ucode=50060000\0" \
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"mtd=IXP4XX-Flash.0:256k(uboot),128k(env),128k(ucode),2048k(linux),-(root)\0" \
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"kerneladdr=50080000\0" \
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"kernelfile=ixdp425/uImage\0" \
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"rootfile=ixdp425/rootfs\0" \
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"rootaddr=50280000\0" \
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"loadaddr=10000\0" \
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"updateboot_ser=mw.b 10000 ff 40000;" \
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" loady ${loadaddr};" \
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" run eraseboot writeboot\0" \
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"updateboot_net=mw.b 10000 ff 40000;" \
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" tftp ${loadaddr} ixdp425/u-boot.bin;" \
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" run eraseboot writeboot\0" \
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"eraseboot=protect off 50000000 5003ffff;" \
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" erase 50000000 5003ffff\0" \
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"writeboot=cp.b 10000 50000000 ${filesize}\0" \
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"updateucode=loady;" \
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" era ${npe_ucode} +${filesize};" \
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" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
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"updateroot=tftp ${loadaddr} ${rootfile};" \
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" era ${rootaddr} +${filesize};" \
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" cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
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"updatekern=tftp ${loadaddr} ${kernelfile};" \
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" era ${kerneladdr} +${filesize};" \
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" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
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"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \
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" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
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"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \
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" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
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"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
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"boot_flash=run flashargs addtty addeth;" \
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" bootm ${kerneladdr}\0" \
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"boot_net=run netargs addtty addeth;" \
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" tftpboot ${loadaddr} ${kernelfile};" \
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" bootm\0"
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/* additions for new relocation code, must be added to all boards */
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
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/*
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* GPIO settings
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*/
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#define CONFIG_SYS_GPIO_UTOPIA_GPIO1 0
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#define CONFIG_SYS_GPIO_UTOPIA_IRQ_N 1
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#define CONFIG_SYS_GPIO_HSS1_IRQ_N 2
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#define CONFIG_SYS_GPIO_HSS0_IRQ_N 3
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#define CONFIG_SYS_GPIO_ETH0_IRQ_N 4
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#define CONFIG_SYS_GPIO_ETH1_IRQ_N 5
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#define CONFIG_SYS_GPIO_I2C_SCL 6
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#define CONFIG_SYS_GPIO_I2C_SDA 7
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#define CONFIG_SYS_GPIO_PCI_INTD_N 8
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#define CONFIG_SYS_GPIO_PCI_INTC_N 9
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#define CONFIG_SYS_GPIO_PCI_INTB_N 10
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#define CONFIG_SYS_GPIO_PCI_INTA_N 11
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#define CONFIG_SYS_GPIO_UTOPIA_GPIO0 12
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#define CONFIG_SYS_GPIO_PCI_RESET_N 13
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#define CONFIG_SYS_GPIO_PCI_CLK 14
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#define CONFIG_SYS_GPIO_EXTBUS_CLK 15
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#endif /* __CONFIG_H */
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