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5c374c9ee1
The Hammerhead platform is built around a AVR32 32-bit microcontroller from Atmel. It offers versatile peripherals, such as ethernet, usb device, usb host etc. The board also incooperates a power supply and is a Power over Ethernet (PoE) Powered Device (PD). Additonally, a Cyclone III FPGA from Altera is integrated on the board. The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which will cover even the most exceptional need of memory bandwidth. Together with the onboard video decoder the board is ready for video processing. For more information see: http:///www.miromico.com/hammerhead Signed-off-by: Julien May <mailinglist@miromico.ch> [haavard.skinnemoen@atmel.com: various small fixes and adaptions] Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
90 lines
2.4 KiB
C
90 lines
2.4 KiB
C
/*
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* Copyright (C) 2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_AVR32_ARCH_CLK_H__
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#define __ASM_AVR32_ARCH_CLK_H__
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#include <asm/arch/chip-features.h>
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#ifdef CONFIG_PLL
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#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
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#else
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#define MAIN_CLK_RATE (CFG_OSC0_HZ)
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#endif
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static inline unsigned long get_cpu_clk_rate(void)
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{
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return MAIN_CLK_RATE >> CFG_CLKDIV_CPU;
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}
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static inline unsigned long get_hsb_clk_rate(void)
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{
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return MAIN_CLK_RATE >> CFG_CLKDIV_HSB;
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}
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static inline unsigned long get_pba_clk_rate(void)
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{
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return MAIN_CLK_RATE >> CFG_CLKDIV_PBA;
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}
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static inline unsigned long get_pbb_clk_rate(void)
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{
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return MAIN_CLK_RATE >> CFG_CLKDIV_PBB;
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}
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/* Accessors for specific devices. More will be added as needed. */
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static inline unsigned long get_sdram_clk_rate(void)
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{
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return get_hsb_clk_rate();
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}
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#ifdef AT32AP700x_CHIP_HAS_USART
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static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
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{
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return get_pba_clk_rate();
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}
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#endif
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#ifdef AT32AP700x_CHIP_HAS_MACB
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static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
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{
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return get_pbb_clk_rate();
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}
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static inline unsigned long get_macb_hclk_rate(unsigned int dev_id)
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{
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return get_hsb_clk_rate();
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}
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#endif
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#ifdef AT32AP700x_CHIP_HAS_MMCI
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static inline unsigned long get_mci_clk_rate(void)
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{
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return get_pbb_clk_rate();
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}
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#endif
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#ifdef AT32AP700x_CHIP_HAS_SPI
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static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
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{
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return get_pba_clk_rate();
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}
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#endif
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extern void clk_init(void);
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extern void gclk_init(void) __attribute__((weak));
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/* Board code may need the SDRAM base clock as a compile-time constant */
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#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB)
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#endif /* __ASM_AVR32_ARCH_CLK_H__ */
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