mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
685 lines
17 KiB
C
685 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2009 SAMSUNG Electronics
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* Minkyu Kang <mk7.kang@samsung.com>
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* Jaehoon Chung <jh80.chung@samsung.com>
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* Portions Copyright 2011-2016 NVIDIA Corporation
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*/
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#include <bouncebuf.h>
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <mmc.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch-tegra/tegra_mmc.h>
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struct tegra_mmc_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct tegra_mmc_priv {
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struct tegra_mmc *reg;
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struct reset_ctl reset_ctl;
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struct clk clk;
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struct gpio_desc cd_gpio; /* Change Detect GPIO */
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struct gpio_desc pwr_gpio; /* Power GPIO */
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struct gpio_desc wp_gpio; /* Write Protect GPIO */
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unsigned int version; /* SDHCI spec. version */
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unsigned int clock; /* Current clock (MHz) */
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};
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static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
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unsigned short power)
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{
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u8 pwr = 0;
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debug("%s: power = %x\n", __func__, power);
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if (power != (unsigned short)-1) {
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switch (1 << power) {
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case MMC_VDD_165_195:
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pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
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break;
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case MMC_VDD_29_30:
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case MMC_VDD_30_31:
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pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
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break;
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case MMC_VDD_32_33:
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case MMC_VDD_33_34:
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pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
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break;
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}
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}
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debug("%s: pwr = %X\n", __func__, pwr);
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/* Set the bus voltage first (if any) */
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writeb(pwr, &priv->reg->pwrcon);
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if (pwr == 0)
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return;
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/* Now enable bus power */
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pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
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writeb(pwr, &priv->reg->pwrcon);
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}
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static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv,
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struct mmc_data *data,
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struct bounce_buffer *bbstate)
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{
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unsigned char ctrl;
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debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
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bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
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data->blocksize);
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writel((u32)(unsigned long)bbstate->bounce_buffer, &priv->reg->sysad);
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/*
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* DMASEL[4:3]
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* 00 = Selects SDMA
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* 01 = Reserved
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* 10 = Selects 32-bit Address ADMA2
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* 11 = Selects 64-bit Address ADMA2
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*/
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ctrl = readb(&priv->reg->hostctl);
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ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
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ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
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writeb(ctrl, &priv->reg->hostctl);
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/* We do not handle DMA boundaries, so set it to max (512 KiB) */
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writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize);
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writew(data->blocks, &priv->reg->blkcnt);
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}
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static void tegra_mmc_set_transfer_mode(struct tegra_mmc_priv *priv,
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struct mmc_data *data)
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{
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unsigned short mode;
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debug(" mmc_set_transfer_mode called\n");
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/*
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* TRNMOD
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* MUL1SIN0[5] : Multi/Single Block Select
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* RD1WT0[4] : Data Transfer Direction Select
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* 1 = read
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* 0 = write
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* ENACMD12[2] : Auto CMD12 Enable
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* ENBLKCNT[1] : Block Count Enable
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* ENDMA[0] : DMA Enable
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*/
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mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
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TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
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if (data->blocks > 1)
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mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
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if (data->flags & MMC_DATA_READ)
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mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
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writew(mode, &priv->reg->trnmod);
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}
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static int tegra_mmc_wait_inhibit(struct tegra_mmc_priv *priv,
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struct mmc_cmd *cmd,
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struct mmc_data *data,
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unsigned int timeout)
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{
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/*
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* PRNSTS
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* CMDINHDAT[1] : Command Inhibit (DAT)
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* CMDINHCMD[0] : Command Inhibit (CMD)
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*/
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unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
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/*
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* We shouldn't wait for data inhibit for stop commands, even
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* though they might use busy signaling
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*/
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if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
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mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
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while (readl(&priv->reg->prnsts) & mask) {
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if (timeout == 0) {
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printf("%s: timeout error\n", __func__);
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return -1;
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}
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timeout--;
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udelay(1000);
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}
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return 0;
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}
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static int tegra_mmc_send_cmd_bounced(struct udevice *dev, struct mmc_cmd *cmd,
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struct mmc_data *data,
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struct bounce_buffer *bbstate)
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{
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struct tegra_mmc_priv *priv = dev_get_priv(dev);
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int flags, i;
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int result;
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unsigned int mask = 0;
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unsigned int retry = 0x100000;
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debug(" mmc_send_cmd called\n");
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result = tegra_mmc_wait_inhibit(priv, cmd, data, 10 /* ms */);
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if (result < 0)
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return result;
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if (data)
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tegra_mmc_prepare_data(priv, data, bbstate);
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debug("cmd->arg: %08x\n", cmd->cmdarg);
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writel(cmd->cmdarg, &priv->reg->argument);
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if (data)
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tegra_mmc_set_transfer_mode(priv, data);
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if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
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return -1;
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/*
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* CMDREG
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* CMDIDX[13:8] : Command index
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* DATAPRNT[5] : Data Present Select
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* ENCMDIDX[4] : Command Index Check Enable
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* ENCMDCRC[3] : Command CRC Check Enable
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* RSPTYP[1:0]
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* 00 = No Response
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* 01 = Length 136
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* 10 = Length 48
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* 11 = Length 48 Check busy after response
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*/
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if (!(cmd->resp_type & MMC_RSP_PRESENT))
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flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
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else if (cmd->resp_type & MMC_RSP_136)
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flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
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else if (cmd->resp_type & MMC_RSP_BUSY)
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flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
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else
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flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
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if (cmd->resp_type & MMC_RSP_CRC)
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flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
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if (cmd->resp_type & MMC_RSP_OPCODE)
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flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
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if (data)
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flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
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debug("cmd: %d\n", cmd->cmdidx);
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writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg);
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for (i = 0; i < retry; i++) {
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mask = readl(&priv->reg->norintsts);
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/* Command Complete */
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if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
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if (!data)
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writel(mask, &priv->reg->norintsts);
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break;
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}
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}
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if (i == retry) {
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printf("%s: waiting for status update\n", __func__);
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writel(mask, &priv->reg->norintsts);
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return -ETIMEDOUT;
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}
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if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
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/* Timeout Error */
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debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
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writel(mask, &priv->reg->norintsts);
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return -ETIMEDOUT;
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} else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
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/* Error Interrupt */
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debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
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writel(mask, &priv->reg->norintsts);
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return -1;
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}
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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if (cmd->resp_type & MMC_RSP_136) {
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/* CRC is stripped so we need to do some shifting. */
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for (i = 0; i < 4; i++) {
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unsigned long offset = (unsigned long)
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(&priv->reg->rspreg3 - i);
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cmd->response[i] = readl(offset) << 8;
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if (i != 3) {
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cmd->response[i] |=
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readb(offset - 1);
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}
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debug("cmd->resp[%d]: %08x\n",
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i, cmd->response[i]);
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}
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} else if (cmd->resp_type & MMC_RSP_BUSY) {
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for (i = 0; i < retry; i++) {
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/* PRNTDATA[23:20] : DAT[3:0] Line Signal */
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if (readl(&priv->reg->prnsts)
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& (1 << 20)) /* DAT[0] */
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break;
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}
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if (i == retry) {
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printf("%s: card is still busy\n", __func__);
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writel(mask, &priv->reg->norintsts);
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return -ETIMEDOUT;
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}
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cmd->response[0] = readl(&priv->reg->rspreg0);
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debug("cmd->resp[0]: %08x\n", cmd->response[0]);
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} else {
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cmd->response[0] = readl(&priv->reg->rspreg0);
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debug("cmd->resp[0]: %08x\n", cmd->response[0]);
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}
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}
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if (data) {
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unsigned long start = get_timer(0);
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while (1) {
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mask = readl(&priv->reg->norintsts);
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if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
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/* Error Interrupt */
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writel(mask, &priv->reg->norintsts);
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printf("%s: error during transfer: 0x%08x\n",
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__func__, mask);
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return -1;
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} else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
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/*
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* DMA Interrupt, restart the transfer where
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* it was interrupted.
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*/
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unsigned int address = readl(&priv->reg->sysad);
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debug("DMA end\n");
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writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
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&priv->reg->norintsts);
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writel(address, &priv->reg->sysad);
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} else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
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/* Transfer Complete */
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debug("r/w is done\n");
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break;
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} else if (get_timer(start) > 8000UL) {
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writel(mask, &priv->reg->norintsts);
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printf("%s: MMC Timeout\n"
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" Interrupt status 0x%08x\n"
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" Interrupt status enable 0x%08x\n"
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" Interrupt signal enable 0x%08x\n"
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" Present status 0x%08x\n",
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__func__, mask,
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readl(&priv->reg->norintstsen),
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readl(&priv->reg->norintsigen),
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readl(&priv->reg->prnsts));
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return -1;
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}
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}
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writel(mask, &priv->reg->norintsts);
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}
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udelay(1000);
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return 0;
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}
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static int tegra_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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void *buf;
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unsigned int bbflags;
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size_t len;
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struct bounce_buffer bbstate;
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int ret;
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if (data) {
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if (data->flags & MMC_DATA_READ) {
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buf = data->dest;
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bbflags = GEN_BB_WRITE;
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} else {
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buf = (void *)data->src;
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bbflags = GEN_BB_READ;
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}
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len = data->blocks * data->blocksize;
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bounce_buffer_start(&bbstate, buf, len, bbflags);
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}
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ret = tegra_mmc_send_cmd_bounced(dev, cmd, data, &bbstate);
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if (data)
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bounce_buffer_stop(&bbstate);
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return ret;
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}
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static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock)
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{
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ulong rate;
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int div;
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unsigned short clk;
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unsigned long timeout;
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debug(" mmc_change_clock called\n");
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/*
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* Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
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*/
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if (clock == 0)
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goto out;
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rate = clk_set_rate(&priv->clk, clock);
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div = (rate + clock - 1) / clock;
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debug("div = %d\n", div);
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writew(0, &priv->reg->clkcon);
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/*
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* CLKCON
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* SELFREQ[15:8] : base clock divided by value
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* ENSDCLK[2] : SD Clock Enable
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* STBLINTCLK[1] : Internal Clock Stable
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* ENINTCLK[0] : Internal Clock Enable
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*/
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div >>= 1;
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clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
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TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
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writew(clk, &priv->reg->clkcon);
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/* Wait max 10 ms */
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timeout = 10;
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while (!(readw(&priv->reg->clkcon) &
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TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
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if (timeout == 0) {
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printf("%s: timeout error\n", __func__);
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return;
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}
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timeout--;
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udelay(1000);
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}
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clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
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writew(clk, &priv->reg->clkcon);
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debug("mmc_change_clock: clkcon = %08X\n", clk);
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out:
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priv->clock = clock;
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}
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static int tegra_mmc_set_ios(struct udevice *dev)
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{
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struct tegra_mmc_priv *priv = dev_get_priv(dev);
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struct mmc *mmc = mmc_get_mmc_dev(dev);
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unsigned char ctrl;
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debug(" mmc_set_ios called\n");
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debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
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/* Change clock first */
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tegra_mmc_change_clock(priv, mmc->clock);
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ctrl = readb(&priv->reg->hostctl);
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/*
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* WIDE8[5]
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* 0 = Depend on WIDE4
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* 1 = 8-bit mode
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* WIDE4[1]
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* 1 = 4-bit mode
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* 0 = 1-bit mode
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*/
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if (mmc->bus_width == 8)
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ctrl |= (1 << 5);
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else if (mmc->bus_width == 4)
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ctrl |= (1 << 1);
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else
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ctrl &= ~(1 << 1 | 1 << 5);
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writeb(ctrl, &priv->reg->hostctl);
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debug("mmc_set_ios: hostctl = %08X\n", ctrl);
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return 0;
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}
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static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
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{
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#if defined(CONFIG_TEGRA30)
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u32 val;
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debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg);
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/* Set the pad drive strength for SDMMC1 or 3 only */
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if (priv->reg != (void *)0x78000000 &&
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priv->reg != (void *)0x78000400) {
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debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
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__func__);
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return;
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}
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val = readl(&priv->reg->sdmemcmppadctl);
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val &= 0xFFFFFFF0;
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val |= MEMCOMP_PADCTRL_VREF;
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writel(val, &priv->reg->sdmemcmppadctl);
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val = readl(&priv->reg->autocalcfg);
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val &= 0xFFFF0000;
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val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
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writel(val, &priv->reg->autocalcfg);
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#endif
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}
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static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc)
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{
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unsigned int timeout;
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debug(" mmc_reset called\n");
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/*
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* RSTALL[0] : Software reset for all
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* 1 = reset
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* 0 = work
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*/
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writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &priv->reg->swrst);
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priv->clock = 0;
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/* Wait max 100 ms */
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timeout = 100;
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/* hw clears the bit when it's done */
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while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
|
|
if (timeout == 0) {
|
|
printf("%s: timeout error\n", __func__);
|
|
return;
|
|
}
|
|
timeout--;
|
|
udelay(1000);
|
|
}
|
|
|
|
/* Set SD bus voltage & enable bus power */
|
|
tegra_mmc_set_power(priv, fls(mmc->cfg->voltages) - 1);
|
|
debug("%s: power control = %02X, host control = %02X\n", __func__,
|
|
readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl));
|
|
|
|
/* Make sure SDIO pads are set up */
|
|
tegra_mmc_pad_init(priv);
|
|
}
|
|
|
|
static int tegra_mmc_init(struct udevice *dev)
|
|
{
|
|
struct tegra_mmc_priv *priv = dev_get_priv(dev);
|
|
struct mmc *mmc = mmc_get_mmc_dev(dev);
|
|
unsigned int mask;
|
|
debug(" tegra_mmc_init called\n");
|
|
|
|
tegra_mmc_reset(priv, mmc);
|
|
|
|
#if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)
|
|
/*
|
|
* Disable the external clock loopback and use the internal one on
|
|
* SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
|
|
* bits being set to 0xfffd according to the TRM.
|
|
*
|
|
* TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
|
|
* approach once proper kernel integration made it mainline.
|
|
*/
|
|
if (priv->reg == (void *)0x700b0400) {
|
|
mask = readl(&priv->reg->venmiscctl);
|
|
mask &= ~TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK;
|
|
writel(mask, &priv->reg->venmiscctl);
|
|
}
|
|
#endif
|
|
|
|
priv->version = readw(&priv->reg->hcver);
|
|
debug("host version = %x\n", priv->version);
|
|
|
|
/* mask all */
|
|
writel(0xffffffff, &priv->reg->norintstsen);
|
|
writel(0xffffffff, &priv->reg->norintsigen);
|
|
|
|
writeb(0xe, &priv->reg->timeoutcon); /* TMCLK * 2^27 */
|
|
/*
|
|
* NORMAL Interrupt Status Enable Register init
|
|
* [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
|
|
* [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
|
|
* [3] ENSTADMAINT : DMA boundary interrupt
|
|
* [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
|
|
* [0] ENSTACMDCMPLT : Command Complete Status Enable
|
|
*/
|
|
mask = readl(&priv->reg->norintstsen);
|
|
mask &= ~(0xffff);
|
|
mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
|
|
TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
|
|
TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
|
|
TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
|
|
TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
|
|
writel(mask, &priv->reg->norintstsen);
|
|
|
|
/*
|
|
* NORMAL Interrupt Signal Enable Register init
|
|
* [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
|
|
*/
|
|
mask = readl(&priv->reg->norintsigen);
|
|
mask &= ~(0xffff);
|
|
mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
|
|
writel(mask, &priv->reg->norintsigen);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_mmc_getcd(struct udevice *dev)
|
|
{
|
|
struct tegra_mmc_priv *priv = dev_get_priv(dev);
|
|
|
|
debug("tegra_mmc_getcd called\n");
|
|
|
|
if (dm_gpio_is_valid(&priv->cd_gpio))
|
|
return dm_gpio_get_value(&priv->cd_gpio);
|
|
|
|
return 1;
|
|
}
|
|
|
|
static const struct dm_mmc_ops tegra_mmc_ops = {
|
|
.send_cmd = tegra_mmc_send_cmd,
|
|
.set_ios = tegra_mmc_set_ios,
|
|
.get_cd = tegra_mmc_getcd,
|
|
};
|
|
|
|
static int tegra_mmc_probe(struct udevice *dev)
|
|
{
|
|
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
|
struct tegra_mmc_plat *plat = dev_get_platdata(dev);
|
|
struct tegra_mmc_priv *priv = dev_get_priv(dev);
|
|
struct mmc_config *cfg = &plat->cfg;
|
|
int bus_width, ret;
|
|
|
|
cfg->name = dev->name;
|
|
|
|
bus_width = dev_read_u32_default(dev, "bus-width", 1);
|
|
|
|
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
|
|
cfg->host_caps = 0;
|
|
if (bus_width == 8)
|
|
cfg->host_caps |= MMC_MODE_8BIT;
|
|
if (bus_width >= 4)
|
|
cfg->host_caps |= MMC_MODE_4BIT;
|
|
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
|
|
|
/*
|
|
* min freq is for card identification, and is the highest
|
|
* low-speed SDIO card frequency (actually 400KHz)
|
|
* max freq is highest HS eMMC clock as per the SD/MMC spec
|
|
* (actually 52MHz)
|
|
*/
|
|
cfg->f_min = 375000;
|
|
cfg->f_max = 48000000;
|
|
|
|
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
|
|
|
|
priv->reg = (void *)dev_read_addr(dev);
|
|
|
|
ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
|
|
if (ret) {
|
|
debug("reset_get_by_name() failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
ret = clk_get_by_index(dev, 0, &priv->clk);
|
|
if (ret) {
|
|
debug("clk_get_by_index() failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = reset_assert(&priv->reset_ctl);
|
|
if (ret)
|
|
return ret;
|
|
ret = clk_enable(&priv->clk);
|
|
if (ret)
|
|
return ret;
|
|
ret = clk_set_rate(&priv->clk, 20000000);
|
|
if (IS_ERR_VALUE(ret))
|
|
return ret;
|
|
ret = reset_deassert(&priv->reset_ctl);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* These GPIOs are optional */
|
|
gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
|
|
gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
|
|
gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio,
|
|
GPIOD_IS_OUT);
|
|
if (dm_gpio_is_valid(&priv->pwr_gpio))
|
|
dm_gpio_set_value(&priv->pwr_gpio, 1);
|
|
|
|
upriv->mmc = &plat->mmc;
|
|
|
|
return tegra_mmc_init(dev);
|
|
}
|
|
|
|
static int tegra_mmc_bind(struct udevice *dev)
|
|
{
|
|
struct tegra_mmc_plat *plat = dev_get_platdata(dev);
|
|
|
|
return mmc_bind(dev, &plat->mmc, &plat->cfg);
|
|
}
|
|
|
|
static const struct udevice_id tegra_mmc_ids[] = {
|
|
{ .compatible = "nvidia,tegra20-sdhci" },
|
|
{ .compatible = "nvidia,tegra30-sdhci" },
|
|
{ .compatible = "nvidia,tegra114-sdhci" },
|
|
{ .compatible = "nvidia,tegra124-sdhci" },
|
|
{ .compatible = "nvidia,tegra210-sdhci" },
|
|
{ .compatible = "nvidia,tegra186-sdhci" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(tegra_mmc_drv) = {
|
|
.name = "tegra_mmc",
|
|
.id = UCLASS_MMC,
|
|
.of_match = tegra_mmc_ids,
|
|
.bind = tegra_mmc_bind,
|
|
.probe = tegra_mmc_probe,
|
|
.ops = &tegra_mmc_ops,
|
|
.platdata_auto_alloc_size = sizeof(struct tegra_mmc_plat),
|
|
.priv_auto_alloc_size = sizeof(struct tegra_mmc_priv),
|
|
};
|