mirror of
https://github.com/AsahiLinux/u-boot
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36821b3f55
Using this driver on socfpga gen5 with DM_I2C enabled leads to a data abort
as the 'i2c' reset property cannot be found (the gen5 dtsi does not provide
reset-names).
The actual bug was to check 'if (&priv->reset_ctl)', which is never false.
While at it, convert the driver to use 'reset_get_bulk' instead of looking
at a specific named reset and also make it release the reset on driver
remove before starting the OS.
Fixes: 622597dee4 ("i2c: designware: add reset ctrl to driver")
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
643 lines
15 KiB
C
643 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2009
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*/
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#include <common.h>
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#include <dm.h>
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#include <i2c.h>
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#include <pci.h>
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#include <reset.h>
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#include <asm/io.h>
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#include "designware_i2c.h"
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struct dw_scl_sda_cfg {
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u32 ss_hcnt;
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u32 fs_hcnt;
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u32 ss_lcnt;
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u32 fs_lcnt;
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u32 sda_hold;
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};
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#ifdef CONFIG_X86
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/* BayTrail HCNT/LCNT/SDA hold time */
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static struct dw_scl_sda_cfg byt_config = {
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.ss_hcnt = 0x200,
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.fs_hcnt = 0x55,
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.ss_lcnt = 0x200,
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.fs_lcnt = 0x99,
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.sda_hold = 0x6,
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};
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#endif
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struct dw_i2c {
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struct i2c_regs *regs;
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struct dw_scl_sda_cfg *scl_sda_cfg;
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struct reset_ctl_bulk resets;
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};
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#ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
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static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
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{
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u32 ena = enable ? IC_ENABLE_0B : 0;
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writel(ena, &i2c_base->ic_enable);
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return 0;
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}
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#else
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static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
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{
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u32 ena = enable ? IC_ENABLE_0B : 0;
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int timeout = 100;
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do {
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writel(ena, &i2c_base->ic_enable);
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if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
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return 0;
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/*
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* Wait 10 times the signaling period of the highest I2C
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* transfer supported by the driver (for 400KHz this is
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* 25us) as described in the DesignWare I2C databook.
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*/
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udelay(25);
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} while (timeout--);
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printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
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return -ETIMEDOUT;
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}
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#endif
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/*
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* i2c_set_bus_speed - Set the i2c speed
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* @speed: required i2c speed
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*
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* Set the i2c speed.
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*/
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static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
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struct dw_scl_sda_cfg *scl_sda_cfg,
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unsigned int speed)
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{
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unsigned int cntl;
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unsigned int hcnt, lcnt;
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int i2c_spd;
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if (speed >= I2C_MAX_SPEED)
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i2c_spd = IC_SPEED_MODE_MAX;
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else if (speed >= I2C_FAST_SPEED)
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i2c_spd = IC_SPEED_MODE_FAST;
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else
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i2c_spd = IC_SPEED_MODE_STANDARD;
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/* to set speed cltr must be disabled */
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dw_i2c_enable(i2c_base, false);
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cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
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switch (i2c_spd) {
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#ifndef CONFIG_X86 /* No High-speed for BayTrail yet */
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case IC_SPEED_MODE_MAX:
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cntl |= IC_CON_SPD_SS;
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if (scl_sda_cfg) {
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hcnt = scl_sda_cfg->fs_hcnt;
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lcnt = scl_sda_cfg->fs_lcnt;
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} else {
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hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
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lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
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}
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writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
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writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
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break;
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#endif
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case IC_SPEED_MODE_STANDARD:
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cntl |= IC_CON_SPD_SS;
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if (scl_sda_cfg) {
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hcnt = scl_sda_cfg->ss_hcnt;
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lcnt = scl_sda_cfg->ss_lcnt;
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} else {
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hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
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lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
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}
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writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
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writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
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break;
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case IC_SPEED_MODE_FAST:
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default:
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cntl |= IC_CON_SPD_FS;
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if (scl_sda_cfg) {
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hcnt = scl_sda_cfg->fs_hcnt;
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lcnt = scl_sda_cfg->fs_lcnt;
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} else {
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hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
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lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
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}
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writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
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writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
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break;
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}
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writel(cntl, &i2c_base->ic_con);
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/* Configure SDA Hold Time if required */
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if (scl_sda_cfg)
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writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);
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/* Enable back i2c now speed set */
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dw_i2c_enable(i2c_base, true);
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return 0;
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}
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/*
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* i2c_setaddress - Sets the target slave address
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* @i2c_addr: target i2c address
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*
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* Sets the target slave address.
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*/
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static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
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{
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/* Disable i2c */
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dw_i2c_enable(i2c_base, false);
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writel(i2c_addr, &i2c_base->ic_tar);
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/* Enable i2c */
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dw_i2c_enable(i2c_base, true);
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}
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/*
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* i2c_flush_rxfifo - Flushes the i2c RX FIFO
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*
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* Flushes the i2c RX FIFO
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*/
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static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
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{
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while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
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readl(&i2c_base->ic_cmd_data);
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}
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/*
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* i2c_wait_for_bb - Waits for bus busy
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*
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* Waits for bus busy
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*/
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static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
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{
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unsigned long start_time_bb = get_timer(0);
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while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
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!(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
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/* Evaluate timeout */
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if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
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return 1;
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}
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return 0;
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}
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static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
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int alen)
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{
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if (i2c_wait_for_bb(i2c_base))
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return 1;
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i2c_setaddress(i2c_base, chip);
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while (alen) {
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alen--;
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/* high byte address going out first */
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writel((addr >> (alen * 8)) & 0xff,
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&i2c_base->ic_cmd_data);
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}
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return 0;
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}
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static int i2c_xfer_finish(struct i2c_regs *i2c_base)
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{
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ulong start_stop_det = get_timer(0);
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while (1) {
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if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
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readl(&i2c_base->ic_clr_stop_det);
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break;
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} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
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break;
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}
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}
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if (i2c_wait_for_bb(i2c_base)) {
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printf("Timed out waiting for bus\n");
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return 1;
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}
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i2c_flush_rxfifo(i2c_base);
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return 0;
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}
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/*
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* i2c_read - Read from i2c memory
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* @chip: target i2c address
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* @addr: address to read from
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* @alen:
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* @buffer: buffer for read data
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* @len: no of bytes to be read
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*
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* Read from i2c memory.
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*/
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static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
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int alen, u8 *buffer, int len)
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{
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unsigned long start_time_rx;
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unsigned int active = 0;
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#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
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/*
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* EEPROM chips that implement "address overflow" are ones
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* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
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* address and the extra bits end up in the "chip address"
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* bit slots. This makes a 24WC08 (1Kbyte) chip look like
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* four 256 byte chips.
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*
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* Note that we consider the length of the address field to
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* still be one byte because the extra address bits are
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* hidden in the chip address.
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*/
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dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
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addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
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debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
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addr);
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#endif
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if (i2c_xfer_init(i2c_base, dev, addr, alen))
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return 1;
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start_time_rx = get_timer(0);
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while (len) {
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if (!active) {
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/*
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* Avoid writing to ic_cmd_data multiple times
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* in case this loop spins too quickly and the
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* ic_status RFNE bit isn't set after the first
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* write. Subsequent writes to ic_cmd_data can
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* trigger spurious i2c transfer.
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*/
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if (len == 1)
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writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
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else
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writel(IC_CMD, &i2c_base->ic_cmd_data);
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active = 1;
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}
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if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
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*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
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len--;
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start_time_rx = get_timer(0);
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active = 0;
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} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
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return 1;
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}
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}
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return i2c_xfer_finish(i2c_base);
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}
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/*
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* i2c_write - Write to i2c memory
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* @chip: target i2c address
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* @addr: address to read from
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* @alen:
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* @buffer: buffer for read data
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* @len: no of bytes to be read
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*
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* Write to i2c memory.
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*/
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static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
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int alen, u8 *buffer, int len)
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{
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int nb = len;
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unsigned long start_time_tx;
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#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
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/*
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* EEPROM chips that implement "address overflow" are ones
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* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
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* address and the extra bits end up in the "chip address"
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* bit slots. This makes a 24WC08 (1Kbyte) chip look like
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* four 256 byte chips.
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*
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* Note that we consider the length of the address field to
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* still be one byte because the extra address bits are
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* hidden in the chip address.
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*/
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dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
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addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
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debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
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addr);
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#endif
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if (i2c_xfer_init(i2c_base, dev, addr, alen))
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return 1;
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start_time_tx = get_timer(0);
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while (len) {
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if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
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if (--len == 0) {
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writel(*buffer | IC_STOP,
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&i2c_base->ic_cmd_data);
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} else {
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writel(*buffer, &i2c_base->ic_cmd_data);
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}
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buffer++;
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start_time_tx = get_timer(0);
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} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
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printf("Timed out. i2c write Failed\n");
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return 1;
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}
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}
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return i2c_xfer_finish(i2c_base);
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}
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/*
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* __dw_i2c_init - Init function
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* @speed: required i2c speed
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* @slaveaddr: slave address for the device
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*
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* Initialization function.
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*/
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static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
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{
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int ret;
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/* Disable i2c */
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ret = dw_i2c_enable(i2c_base, false);
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if (ret)
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return ret;
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writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
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&i2c_base->ic_con);
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writel(IC_RX_TL, &i2c_base->ic_rx_tl);
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writel(IC_TX_TL, &i2c_base->ic_tx_tl);
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writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
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#ifndef CONFIG_DM_I2C
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__dw_i2c_set_bus_speed(i2c_base, NULL, speed);
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writel(slaveaddr, &i2c_base->ic_sar);
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#endif
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/* Enable i2c */
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ret = dw_i2c_enable(i2c_base, true);
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if (ret)
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return ret;
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return 0;
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}
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#ifndef CONFIG_DM_I2C
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/*
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* The legacy I2C functions. These need to get removed once
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* all users of this driver are converted to DM.
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*/
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static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
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{
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switch (adap->hwadapnr) {
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#if CONFIG_SYS_I2C_BUS_MAX >= 4
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case 3:
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return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
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#endif
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#if CONFIG_SYS_I2C_BUS_MAX >= 3
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case 2:
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return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
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#endif
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#if CONFIG_SYS_I2C_BUS_MAX >= 2
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case 1:
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return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
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#endif
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case 0:
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return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
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default:
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printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
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}
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return NULL;
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}
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static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
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unsigned int speed)
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{
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adap->speed = speed;
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return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed);
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}
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static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
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{
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__dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
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}
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static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
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int alen, u8 *buffer, int len)
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{
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return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
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}
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static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
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int alen, u8 *buffer, int len)
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{
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return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
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}
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/* dw_i2c_probe - Probe the i2c chip */
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static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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u32 tmp;
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int ret;
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/*
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* Try to read the first location of the chip.
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*/
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ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
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if (ret)
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dw_i2c_init(adap, adap->speed, adap->slaveaddr);
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return ret;
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}
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U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
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dw_i2c_write, dw_i2c_set_bus_speed,
|
|
CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
|
|
|
|
#if CONFIG_SYS_I2C_BUS_MAX >= 2
|
|
U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
|
|
dw_i2c_write, dw_i2c_set_bus_speed,
|
|
CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
|
|
#endif
|
|
|
|
#if CONFIG_SYS_I2C_BUS_MAX >= 3
|
|
U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
|
|
dw_i2c_write, dw_i2c_set_bus_speed,
|
|
CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
|
|
#endif
|
|
|
|
#if CONFIG_SYS_I2C_BUS_MAX >= 4
|
|
U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
|
|
dw_i2c_write, dw_i2c_set_bus_speed,
|
|
CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
|
|
#endif
|
|
|
|
#else /* CONFIG_DM_I2C */
|
|
/* The DM I2C functions */
|
|
|
|
static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
|
|
int nmsgs)
|
|
{
|
|
struct dw_i2c *i2c = dev_get_priv(bus);
|
|
int ret;
|
|
|
|
debug("i2c_xfer: %d messages\n", nmsgs);
|
|
for (; nmsgs > 0; nmsgs--, msg++) {
|
|
debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
|
|
if (msg->flags & I2C_M_RD) {
|
|
ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
|
|
msg->buf, msg->len);
|
|
} else {
|
|
ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
|
|
msg->buf, msg->len);
|
|
}
|
|
if (ret) {
|
|
debug("i2c_write: error sending\n");
|
|
return -EREMOTEIO;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
|
|
{
|
|
struct dw_i2c *i2c = dev_get_priv(bus);
|
|
|
|
return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed);
|
|
}
|
|
|
|
static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
|
|
uint chip_flags)
|
|
{
|
|
struct dw_i2c *i2c = dev_get_priv(bus);
|
|
struct i2c_regs *i2c_base = i2c->regs;
|
|
u32 tmp;
|
|
int ret;
|
|
|
|
/* Try to read the first location of the chip */
|
|
ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
|
|
if (ret)
|
|
__dw_i2c_init(i2c_base, 0, 0);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int designware_i2c_probe(struct udevice *bus)
|
|
{
|
|
struct dw_i2c *priv = dev_get_priv(bus);
|
|
int ret;
|
|
|
|
if (device_is_on_pci_bus(bus)) {
|
|
#ifdef CONFIG_DM_PCI
|
|
/* Save base address from PCI BAR */
|
|
priv->regs = (struct i2c_regs *)
|
|
dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
|
|
#ifdef CONFIG_X86
|
|
/* Use BayTrail specific timing values */
|
|
priv->scl_sda_cfg = &byt_config;
|
|
#endif
|
|
#endif
|
|
} else {
|
|
priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
|
|
}
|
|
|
|
ret = reset_get_bulk(bus, &priv->resets);
|
|
if (ret)
|
|
dev_warn(bus, "Can't get reset: %d\n", ret);
|
|
else
|
|
reset_deassert_bulk(&priv->resets);
|
|
|
|
return __dw_i2c_init(priv->regs, 0, 0);
|
|
}
|
|
|
|
static int designware_i2c_remove(struct udevice *dev)
|
|
{
|
|
struct dw_i2c *priv = dev_get_priv(dev);
|
|
|
|
return reset_release_bulk(&priv->resets);
|
|
}
|
|
|
|
static int designware_i2c_bind(struct udevice *dev)
|
|
{
|
|
static int num_cards;
|
|
char name[20];
|
|
|
|
/* Create a unique device name for PCI type devices */
|
|
if (device_is_on_pci_bus(dev)) {
|
|
/*
|
|
* ToDo:
|
|
* Setting req_seq in the driver is probably not recommended.
|
|
* But without a DT alias the number is not configured. And
|
|
* using this driver is impossible for PCIe I2C devices.
|
|
* This can be removed, once a better (correct) way for this
|
|
* is found and implemented.
|
|
*/
|
|
dev->req_seq = num_cards;
|
|
sprintf(name, "i2c_designware#%u", num_cards++);
|
|
device_set_name(dev, name);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_i2c_ops designware_i2c_ops = {
|
|
.xfer = designware_i2c_xfer,
|
|
.probe_chip = designware_i2c_probe_chip,
|
|
.set_bus_speed = designware_i2c_set_bus_speed,
|
|
};
|
|
|
|
static const struct udevice_id designware_i2c_ids[] = {
|
|
{ .compatible = "snps,designware-i2c" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(i2c_designware) = {
|
|
.name = "i2c_designware",
|
|
.id = UCLASS_I2C,
|
|
.of_match = designware_i2c_ids,
|
|
.bind = designware_i2c_bind,
|
|
.probe = designware_i2c_probe,
|
|
.priv_auto_alloc_size = sizeof(struct dw_i2c),
|
|
.remove = designware_i2c_remove,
|
|
.flags = DM_FLAG_OS_PREPARE,
|
|
.ops = &designware_i2c_ops,
|
|
};
|
|
|
|
#ifdef CONFIG_X86
|
|
static struct pci_device_id designware_pci_supported[] = {
|
|
/* Intel BayTrail has 7 I2C controller located on the PCI bus */
|
|
{ PCI_VDEVICE(INTEL, 0x0f41) },
|
|
{ PCI_VDEVICE(INTEL, 0x0f42) },
|
|
{ PCI_VDEVICE(INTEL, 0x0f43) },
|
|
{ PCI_VDEVICE(INTEL, 0x0f44) },
|
|
{ PCI_VDEVICE(INTEL, 0x0f45) },
|
|
{ PCI_VDEVICE(INTEL, 0x0f46) },
|
|
{ PCI_VDEVICE(INTEL, 0x0f47) },
|
|
{},
|
|
};
|
|
|
|
U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported);
|
|
#endif
|
|
|
|
#endif /* CONFIG_DM_I2C */
|