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https://github.com/AsahiLinux/u-boot
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aa6e94deab
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
420 lines
9.5 KiB
C
420 lines
9.5 KiB
C
// SPDX-License-Identifier: (GPL-2.0+)
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/*
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* suniv DRAM initialization
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*
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* Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
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*
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* Based on xboot's arch/arm32/mach-f1c100s/sys-dram.c, which is:
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*
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* Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/dram.h>
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#include <asm/arch/gpio.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <hang.h>
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#define SDR_T_CAS (0x2)
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#define SDR_T_RAS (0x8)
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#define SDR_T_RCD (0x3)
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#define SDR_T_RP (0x3)
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#define SDR_T_WR (0x3)
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#define SDR_T_RFC (0xd)
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#define SDR_T_XSR (0xf9)
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#define SDR_T_RC (0xb)
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#define SDR_T_INIT (0x8)
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#define SDR_T_INIT_REF (0x7)
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#define SDR_T_WTR (0x2)
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#define SDR_T_RRD (0x2)
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#define SDR_T_XP (0x0)
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enum dram_type {
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DRAM_TYPE_SDR = 0,
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DRAM_TYPE_DDR = 1,
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/* Not supported yet. */
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DRAM_TYPE_MDDR = 2,
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};
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struct dram_para {
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u32 size; /* dram size (unit: MByte) */
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u32 clk; /* dram work clock (unit: MHz) */
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u32 access_mode; /* 0: interleave mode 1: sequence mode */
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u32 cs_num; /* dram chip count 1: one chip 2: two chip */
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u32 ddr8_remap; /* for 8bits data width DDR 0: normal 1: 8bits */
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enum dram_type sdr_ddr;
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u32 bwidth; /* dram bus width */
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u32 col_width; /* column address width */
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u32 row_width; /* row address width */
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u32 bank_size; /* dram bank count */
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u32 cas; /* dram cas */
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};
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struct dram_para suniv_dram_para = {
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.size = 32,
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.clk = 156,
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.access_mode = 1,
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.cs_num = 1,
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.ddr8_remap = 0,
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.sdr_ddr = DRAM_TYPE_DDR,
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.bwidth = 16,
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.col_width = 10,
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.row_width = 13,
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.bank_size = 4,
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.cas = 0x3,
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};
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static int dram_initial(void)
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{
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unsigned int time = 0xffffff;
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setbits_le32(SUNXI_DRAMC_BASE + DRAM_SCTLR, 0x1);
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while ((readl(SUNXI_DRAMC_BASE + DRAM_SCTLR) & 0x1) && time--) {
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if (time == 0)
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return 0;
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}
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return 1;
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}
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static int dram_delay_scan(void)
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{
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unsigned int time = 0xffffff;
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setbits_le32(SUNXI_DRAMC_BASE + DRAM_DDLYR, 0x1);
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while ((readl(SUNXI_DRAMC_BASE + DRAM_DDLYR) & 0x1) && time--) {
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if (time == 0)
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return 0;
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}
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return 1;
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}
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static void dram_set_autofresh_cycle(u32 clk)
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{
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u32 val = 0;
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u32 row = 0;
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u32 temp = 0;
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row = readl(SUNXI_DRAMC_BASE + DRAM_SCONR);
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row &= 0x1e0;
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row >>= 0x5;
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if (row == 0xc) {
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if (clk >= 1000000) {
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temp = clk + (clk >> 3) + (clk >> 4) + (clk >> 5);
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while (temp >= (10000000 >> 6)) {
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temp -= (10000000 >> 6);
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val++;
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}
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} else {
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val = (clk * 499) >> 6;
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}
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} else if (row == 0xb) {
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if (clk >= 1000000) {
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temp = clk + (clk >> 3) + (clk >> 4) + (clk >> 5);
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while (temp >= (10000000 >> 7)) {
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temp -= (10000000 >> 7);
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val++;
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}
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} else {
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val = (clk * 499) >> 5;
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}
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}
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writel(val, SUNXI_DRAMC_BASE + DRAM_SREFR);
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}
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static int dram_para_setup(struct dram_para *para)
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{
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u32 val = 0;
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val = (para->ddr8_remap) | (0x1 << 1) |
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((para->bank_size >> 2) << 3) |
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((para->cs_num >> 1) << 4) |
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((para->row_width - 1) << 5) |
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((para->col_width - 1) << 9) |
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((para->sdr_ddr ? (para->bwidth >> 4) : (para->bwidth >> 5)) << 13) |
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(para->access_mode << 15) |
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(para->sdr_ddr << 16);
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writel(val, SUNXI_DRAMC_BASE + DRAM_SCONR);
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setbits_le32(SUNXI_DRAMC_BASE + DRAM_SCTLR, 0x1 << 19);
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return dram_initial();
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}
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static u32 dram_check_delay(u32 bwidth)
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{
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u32 dsize;
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int i, j;
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u32 num = 0;
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u32 dflag = 0;
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dsize = ((bwidth == 16) ? 4 : 2);
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for (i = 0; i < dsize; i++) {
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if (i == 0)
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dflag = readl(SUNXI_DRAMC_BASE + DRAM_DRPTR0);
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else if (i == 1)
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dflag = readl(SUNXI_DRAMC_BASE + DRAM_DRPTR1);
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else if (i == 2)
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dflag = readl(SUNXI_DRAMC_BASE + DRAM_DRPTR2);
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else if (i == 3)
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dflag = readl(SUNXI_DRAMC_BASE + DRAM_DRPTR3);
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for (j = 0; j < 32; j++) {
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if (dflag & 0x1)
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num++;
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dflag >>= 1;
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}
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}
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return num;
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}
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static int sdr_readpipe_scan(void)
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{
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u32 k = 0;
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for (k = 0; k < 32; k++)
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writel(k, CFG_SYS_SDRAM_BASE + 4 * k);
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for (k = 0; k < 32; k++) {
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if (readl(CFG_SYS_SDRAM_BASE + 4 * k) != k)
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return 0;
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}
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return 1;
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}
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static u32 sdr_readpipe_select(void)
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{
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u32 value = 0;
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u32 i = 0;
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for (i = 0; i < 8; i++) {
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clrsetbits_le32(SUNXI_DRAMC_BASE + DRAM_SCTLR,
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0x7 << 6, i << 6);
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if (sdr_readpipe_scan()) {
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value = i;
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return value;
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}
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}
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return value;
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}
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static u32 dram_check_type(struct dram_para *para)
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{
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u32 times = 0;
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int i;
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for (i = 0; i < 8; i++) {
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clrsetbits_le32(SUNXI_DRAMC_BASE + DRAM_SCTLR,
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0x7 << 6, i << 6);
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dram_delay_scan();
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if (readl(SUNXI_DRAMC_BASE + DRAM_DDLYR) & 0x30)
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times++;
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}
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if (times == 8) {
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para->sdr_ddr = DRAM_TYPE_SDR;
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return 0;
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}
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para->sdr_ddr = DRAM_TYPE_DDR;
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return 1;
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}
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static u32 dram_scan_readpipe(struct dram_para *para)
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{
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u32 rp_best = 0, rp_val = 0;
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u32 readpipe[8];
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int i;
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if (para->sdr_ddr == DRAM_TYPE_DDR) {
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for (i = 0; i < 8; i++) {
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clrsetbits_le32(SUNXI_DRAMC_BASE + DRAM_SCTLR,
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0x7 << 6, i << 6);
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dram_delay_scan();
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readpipe[i] = 0;
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if ((((readl(SUNXI_DRAMC_BASE + DRAM_DDLYR) >> 4) & 0x3) == 0x0) &&
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(((readl(SUNXI_DRAMC_BASE + DRAM_DDLYR) >> 4) & 0x1) == 0x0))
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readpipe[i] = dram_check_delay(para->bwidth);
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if (rp_val < readpipe[i]) {
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rp_val = readpipe[i];
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rp_best = i;
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}
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}
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clrsetbits_le32(SUNXI_DRAMC_BASE + DRAM_SCTLR,
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0x7 << 6, rp_best << 6);
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dram_delay_scan();
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} else {
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clrbits_le32(SUNXI_DRAMC_BASE + DRAM_SCONR,
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(0x1 << 16) | (0x3 << 13));
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rp_best = sdr_readpipe_select();
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clrsetbits_le32(SUNXI_DRAMC_BASE + DRAM_SCTLR,
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0x7 << 6, rp_best << 6);
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}
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return 0;
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}
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static u32 dram_get_dram_size(struct dram_para *para)
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{
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u32 colflag = 10, rowflag = 13;
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u32 val1 = 0;
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u32 count = 0;
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u32 addr1, addr2;
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int i;
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para->col_width = colflag;
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para->row_width = rowflag;
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dram_para_setup(para);
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dram_scan_readpipe(para);
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for (i = 0; i < 32; i++) {
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*((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11;
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*((u8 *)(CFG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22;
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}
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for (i = 0; i < 32; i++) {
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val1 = *((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i));
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if (val1 == 0x22)
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count++;
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}
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if (count == 32)
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colflag = 9;
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else
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colflag = 10;
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count = 0;
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para->col_width = colflag;
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para->row_width = rowflag;
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dram_para_setup(para);
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if (colflag == 10) {
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addr1 = CFG_SYS_SDRAM_BASE + 0x400000;
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addr2 = CFG_SYS_SDRAM_BASE + 0xc00000;
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} else {
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addr1 = CFG_SYS_SDRAM_BASE + 0x200000;
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addr2 = CFG_SYS_SDRAM_BASE + 0x600000;
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}
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for (i = 0; i < 32; i++) {
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*((u8 *)(addr1 + i)) = 0x33;
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*((u8 *)(addr2 + i)) = 0x44;
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}
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for (i = 0; i < 32; i++) {
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val1 = *((u8 *)(addr1 + i));
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if (val1 == 0x44)
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count++;
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}
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if (count == 32)
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rowflag = 12;
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else
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rowflag = 13;
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para->col_width = colflag;
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para->row_width = rowflag;
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if (para->row_width != 13)
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para->size = 16;
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else if (para->col_width == 10)
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para->size = 64;
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else
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para->size = 32;
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dram_set_autofresh_cycle(para->clk);
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para->access_mode = 0;
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dram_para_setup(para);
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return 0;
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}
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static void simple_dram_check(void)
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{
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volatile u32 *dram = (u32 *)CFG_SYS_SDRAM_BASE;
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int i;
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for (i = 0; i < 0x40; i++)
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dram[i] = i;
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for (i = 0; i < 0x40; i++) {
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if (dram[i] != i) {
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printf("DRAM initialization failed: dram[0x%x] != 0x%x.", i, dram[i]);
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hang();
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}
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}
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for (i = 0; i < 0x10000; i += 0x40)
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dram[i] = i;
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for (i = 0; i < 0x10000; i += 0x40) {
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if (dram[i] != i) {
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printf("DRAM initialization failed: dram[0x%x] != 0x%x.", i, dram[i]);
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hang();
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}
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}
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}
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static void do_dram_init(struct dram_para *para)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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u32 val;
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u8 m; /* PLL_DDR clock factor */
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sunxi_gpio_set_cfgpin(SUNXI_GPB(3), 0x7);
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mdelay(5);
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/* TODO: dig out what's them... some analog register? */
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if ((para->cas >> 3) & 0x1)
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setbits_le32(SUNXI_PIO_BASE + 0x2c4, (0x1 << 23) | (0x20 << 17));
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if (para->clk >= 144 && para->clk <= 180)
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writel(0xaaa, SUNXI_PIO_BASE + 0x2c0);
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if (para->clk >= 180)
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writel(0xfff, SUNXI_PIO_BASE + 0x2c0);
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if (para->cas & BIT(4))
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writel(0xd1303333, &ccm->pll5_pattern_cfg);
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else if (para->cas & BIT(5))
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writel(0xcce06666, &ccm->pll5_pattern_cfg);
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else if (para->cas & BIT(6))
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writel(0xc8909999, &ccm->pll5_pattern_cfg);
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else if (para->cas & BIT(7))
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writel(0xc440cccc, &ccm->pll5_pattern_cfg);
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if (para->clk <= 96)
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m = 2;
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else
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m = 1;
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val = CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD |
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CCM_PLL5_CTRL_N((para->clk * 2) / (24 / m)) |
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CCM_PLL5_CTRL_K(1) | CCM_PLL5_CTRL_M(m);
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if (para->cas & GENMASK(7, 4))
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val |= CCM_PLL5_CTRL_SIGMA_DELTA_EN;
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writel(val, &ccm->pll5_cfg);
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setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_UPD);
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mctl_await_completion(&ccm->pll5_cfg, BIT(28), BIT(28));
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mdelay(5);
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setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_MCTL));
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clrbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_RESET_OFFSET_MCTL));
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udelay(50);
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setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_RESET_OFFSET_MCTL));
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clrsetbits_le32(SUNXI_PIO_BASE + 0x2c4, (1 << 16),
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((para->sdr_ddr == DRAM_TYPE_DDR) << 16));
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val = (SDR_T_CAS << 0) | (SDR_T_RAS << 3) | (SDR_T_RCD << 7) |
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(SDR_T_RP << 10) | (SDR_T_WR << 13) | (SDR_T_RFC << 15) |
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(SDR_T_XSR << 19) | (SDR_T_RC << 28);
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writel(val, SUNXI_DRAMC_BASE + DRAM_STMG0R);
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val = (SDR_T_INIT << 0) | (SDR_T_INIT_REF << 16) | (SDR_T_WTR << 20) |
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(SDR_T_RRD << 22) | (SDR_T_XP << 25);
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writel(val, SUNXI_DRAMC_BASE + DRAM_STMG1R);
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dram_para_setup(para);
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dram_check_type(para);
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clrsetbits_le32(SUNXI_PIO_BASE + 0x2c4, (1 << 16),
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((para->sdr_ddr == DRAM_TYPE_DDR) << 16));
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dram_set_autofresh_cycle(para->clk);
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dram_scan_readpipe(para);
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dram_get_dram_size(para);
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simple_dram_check();
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}
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unsigned long sunxi_dram_init(void)
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{
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do_dram_init(&suniv_dram_para);
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return suniv_dram_para.size * 1024 * 1024;
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}
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