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dd0ebfe8a4
The latest SOM specification doesn't enforce certain MIO lines allocated for ethernet or ethernet controller itself. That's why remove comment about it which is likely there from early version of specification. Also removed the same comment from pinctrl node. It is clear that it has to be defined for different carrier cards. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/9406377bf2c391ac0200670511bd6b0edb097c96.1676880543.git.michal.simek@amd.com
389 lines
7.9 KiB
Text
389 lines
7.9 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for KR260 revA Carrier Card
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*
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* (C) Copyright 2021, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/net/ti-dp83867.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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/dts-v1/;
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/plugin/;
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&{/} {
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compatible = "xlnx,zynqmp-sk-kr260-revA",
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"xlnx,zynqmp-sk-kr260", "xlnx,zynqmp";
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model = "ZynqMP KR260 revA";
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ina260-u14 {
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compatible = "iio-hwmon";
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io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
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};
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si5332_0: si5332_0 { /* u17 - GEM0/1 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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si5332_1: si5332_1 { /* u17 - DP */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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};
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si5332_2: si5332_2 { /* u17 - USB */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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};
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si5332_3: si5332_3 { /* u17 - SFP+ */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <156250000>;
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};
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si5332_4: si5332_4 { /* u17 - GEM2 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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si5332_5: si5332_5 { /* u17 - GEM3 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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};
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&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1_default>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
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u14: ina260@40 { /* u14 */
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compatible = "ti,ina260";
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#io-channel-cells = <1>;
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label = "ina260-u14";
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reg = <0x40>;
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};
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slg7xl45106: gpio@11 { /* u19 - reset logic */
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compatible = "dlg,slg7xl45106";
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reg = <0x11>;
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label = "resetchip";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B",
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"SD_RESET_B", "USB0_HUB_RESET_B",
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"USB1_HUB_RESET_B", "PS_GEM0_RESET_B",
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"PS_GEM1_RESET_B", "";
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};
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i2c-mux@74 { /* u18 */
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compatible = "nxp,pca9546";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x74>;
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usbhub_i2c0: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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usbhub_i2c1: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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/* Bus 2/3 are not connected */
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};
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/* si5332@6a - u17 - clock-generator */
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};
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/* GEM SGMII/DP and USB 3.0 */
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&psgtr {
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status = "okay";
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/* gem0/1, dp, usb */
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clocks = <&si5332_0>, <&si5332_1>, <&si5332_2>;
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clock-names = "ref0", "ref1", "ref2";
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};
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&zynqmp_dpsub {
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status = "okay";
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phy-names = "dp-phy0";
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phys = <&psgtr 1 PHY_TYPE_DP 0 1>;
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assigned-clock-rates = <27000000>, <25000000>, <300000000>;
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};
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&zynqmp_dpdma {
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status = "okay";
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assigned-clock-rates = <600000000>;
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};
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&usb0 { /* mio52 - mio63 */
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0_default>;
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phy-names = "usb3-phy";
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phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
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reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
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assigned-clock-rates = <250000000>, <20000000>;
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usbhub0: usb-hub { /* u43 */
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i2c-bus = <&usbhub_i2c0>;
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compatible = "microchip,usb5744";
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reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
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};
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usb2244: usb-sd { /* u38 */
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compatible = "microchip,usb2244";
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reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>;
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};
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};
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&dwc3_0 {
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status = "okay";
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dr_mode = "host";
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snps,usb3_lpm_capable;
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maximum-speed = "super-speed";
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};
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&usb1 { /* mio64 - mio75 */
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1_default>;
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phy-names = "usb3-phy";
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phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
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reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>;
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assigned-clock-rates = <250000000>, <20000000>;
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usbhub1: usb-hub { /* u84 */
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i2c-bus = <&usbhub_i2c1>;
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compatible = "microchip,usb5744";
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reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
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};
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};
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&dwc3_1 {
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status = "okay";
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dr_mode = "host";
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snps,usb3_lpm_capable;
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maximum-speed = "super-speed";
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};
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&gem0 { /* mdio mio50/51 */
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status = "okay";
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phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
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phy-handle = <&phy0>;
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phy-mode = "sgmii";
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is-internal-pcspma;
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};
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&gem1 { /* mdio mio50/51, gem mio38 - mio49 */
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gem1_default>;
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phy-handle = <&phy1>;
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phy-mode = "rgmii-id";
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@4 { /* u81 */
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#phy-cells = <1>;
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compatible = "ethernet-phy-id2000.a231";
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reg = <4>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,dp83867-rxctrl-strap-quirk;
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reset-assert-us = <100>;
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reset-deassert-us = <280>;
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reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>;
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};
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phy1: ethernet-phy@8 { /* u36 */
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#phy-cells = <1>;
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compatible = "ethernet-phy-id2000.a231";
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reg = <8>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,dp83867-rxctrl-strap-quirk;
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reset-assert-us = <100>;
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reset-deassert-us = <280>;
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reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_LOW>;
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};
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};
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};
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/* gem2/gem3 via PL with phys u79@2 and u80@3 */
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&pinctrl0 {
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status = "okay";
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pinctrl_uart1_default: uart1-default {
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conf {
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groups = "uart1_9_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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drive-strength = <12>;
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};
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conf-rx {
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pins = "MIO37";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO36";
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bias-disable;
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};
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mux {
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groups = "uart1_9_grp";
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function = "uart1";
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};
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};
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pinctrl_i2c1_default: i2c1-default {
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conf {
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groups = "i2c1_6_grp";
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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mux {
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groups = "i2c1_6_grp";
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function = "i2c1";
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};
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};
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pinctrl_i2c1_gpio: i2c1-gpio {
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conf {
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groups = "gpio0_24_grp", "gpio0_25_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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mux {
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groups = "gpio0_24_grp", "gpio0_25_grp";
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function = "gpio0";
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};
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};
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pinctrl_gem1_default: gem1-default {
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conf {
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groups = "ethernet1_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO44", "MIO46", "MIO48";
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bias-high-impedance;
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low-power-disable;
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};
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conf-bootstrap {
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pins = "MIO45", "MIO47", "MIO49";
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bias-disable;
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low-power-disable;
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};
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conf-tx {
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pins = "MIO38", "MIO39", "MIO40",
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"MIO41", "MIO42", "MIO43";
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bias-disable;
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low-power-enable;
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};
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conf-mdio {
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groups = "mdio1_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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bias-disable;
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};
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mux-mdio {
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function = "mdio1";
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groups = "mdio1_0_grp";
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};
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mux {
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function = "ethernet1";
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groups = "ethernet1_0_grp";
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};
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};
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pinctrl_usb0_default: usb0-default {
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conf {
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groups = "usb0_0_grp";
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO52", "MIO53", "MIO55";
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bias-high-impedance;
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drive-strength = <12>;
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slew-rate = <SLEW_RATE_FAST>;
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};
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conf-tx {
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pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
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"MIO60", "MIO61", "MIO62", "MIO63";
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bias-disable;
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drive-strength = <4>;
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slew-rate = <SLEW_RATE_SLOW>;
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};
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mux {
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groups = "usb0_0_grp";
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function = "usb0";
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};
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};
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pinctrl_usb1_default: usb1-default {
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conf {
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groups = "usb1_0_grp";
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO64", "MIO65", "MIO67";
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bias-high-impedance;
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drive-strength = <12>;
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slew-rate = <SLEW_RATE_FAST>;
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};
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conf-tx {
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pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
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"MIO72", "MIO73", "MIO74", "MIO75";
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bias-disable;
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drive-strength = <4>;
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slew-rate = <SLEW_RATE_SLOW>;
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};
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mux {
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groups = "usb1_0_grp";
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function = "usb1";
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};
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};
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_default>;
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};
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