mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-12 07:57:21 +00:00
051451ad83
Synchronize devicetree sources with Linux v6.2. - Use GIC interrupt definitions - Add reg properties in USB-glue and SoC-glue node - Fix node names to follow the generic names list in DT specification - Add L2 cache and AHCI nodes - Update nand and pcie nodes - And some trivial fixes Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Marek Vasut <marex@denx.de>
162 lines
2 KiB
Text
162 lines
2 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
|
//
|
|
// Device Tree Source for UniPhier PXs3 Reference Board
|
|
//
|
|
// Copyright (C) 2017 Socionext Inc.
|
|
// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
|
|
/dts-v1/;
|
|
#include "uniphier-pxs3.dtsi"
|
|
#include "uniphier-support-card.dtsi"
|
|
|
|
/ {
|
|
model = "UniPhier PXs3 Reference Board";
|
|
compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3";
|
|
|
|
chosen {
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
|
|
aliases {
|
|
serial0 = &serial0;
|
|
serial1 = &serialsc;
|
|
serial2 = &serial2;
|
|
serial3 = &serial3;
|
|
i2c0 = &i2c0;
|
|
i2c1 = &i2c1;
|
|
i2c2 = &i2c2;
|
|
i2c3 = &i2c3;
|
|
i2c6 = &i2c6;
|
|
spi0 = &spi0;
|
|
spi1 = &spi1;
|
|
ethernet0 = ð0;
|
|
ethernet1 = ð1;
|
|
};
|
|
|
|
memory@80000000 {
|
|
device_type = "memory";
|
|
reg = <0 0x80000000 0 0xa0000000>;
|
|
};
|
|
};
|
|
|
|
ðsc {
|
|
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
&serialsc {
|
|
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
&spi0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&spi1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&serial0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&serial2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&serial3 {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpio {
|
|
xirq4-hog {
|
|
gpio-hog;
|
|
gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
|
|
input;
|
|
};
|
|
};
|
|
|
|
&i2c0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c3 {
|
|
status = "okay";
|
|
};
|
|
|
|
&sd {
|
|
status = "okay";
|
|
};
|
|
|
|
ð0 {
|
|
status = "okay";
|
|
phy-handle = <ðphy0>;
|
|
};
|
|
|
|
&mdio0 {
|
|
ethphy0: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
ð1 {
|
|
status = "okay";
|
|
phy-handle = <ðphy1>;
|
|
};
|
|
|
|
&mdio1 {
|
|
ethphy1: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
&usb0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&pcie {
|
|
status = "okay";
|
|
};
|
|
|
|
&nand {
|
|
status = "okay";
|
|
|
|
nand@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
&ahci0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&ahci1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&pinctrl_ether_rgmii {
|
|
tx {
|
|
pins = "RGMII0_TXCLK", "RGMII0_TXD0", "RGMII0_TXD1",
|
|
"RGMII0_TXD2", "RGMII0_TXD3", "RGMII0_TXCTL";
|
|
drive-strength = <9>;
|
|
};
|
|
};
|
|
|
|
&pinctrl_ether1_rgmii {
|
|
tx {
|
|
pins = "RGMII1_TXCLK", "RGMII1_TXD0", "RGMII1_TXD1",
|
|
"RGMII1_TXD2", "RGMII1_TXD3", "RGMII1_TXCTL";
|
|
drive-strength = <9>;
|
|
};
|
|
};
|