mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-12 07:57:21 +00:00
8c103c33fb
Now that Linux has accepted these tags, move the device tree files in U-Boot over to use them. Signed-off-by: Simon Glass <sjg@chromium.org>
241 lines
6.2 KiB
Text
241 lines
6.2 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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#include <stm32f7-u-boot.dtsi>
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/{
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chosen {
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bootargs = "root=/dev/ram rdinit=/linuxrc";
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};
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aliases {
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/* Aliases for gpios so as to use sequence */
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gpio0 = &gpioa;
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gpio1 = &gpiob;
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gpio2 = &gpioc;
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gpio3 = &gpiod;
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gpio4 = &gpioe;
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gpio5 = &gpiof;
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gpio6 = &gpiog;
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gpio7 = &gpioh;
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gpio8 = &gpioi;
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gpio9 = &gpioj;
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gpio10 = &gpiok;
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mmc0 = &sdio1;
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spi0 = &qspi;
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};
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backlight: backlight {
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compatible = "gpio-backlight";
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gpios = <&gpiok 3 0>;
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status = "okay";
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};
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button1 {
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compatible = "st,button1";
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button-gpio = <&gpioi 11 0>;
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};
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led1 {
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compatible = "st,led1";
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led-gpio = <&gpioi 1 0>;
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};
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panel-rgb@0 {
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compatible = "simple-panel";
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backlight = <&backlight>;
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enable-gpios = <&gpioi 12 0>;
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status = "okay";
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display-timings {
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timing@0 {
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clock-frequency = <9000000>;
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hactive = <480>;
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vactive = <272>;
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hfront-porch = <2>;
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hback-porch = <2>;
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hsync-len = <41>;
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vfront-porch = <2>;
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vback-porch = <2>;
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vsync-len = <10>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <1>;
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pixelclk-active = <1>;
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};
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};
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};
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soc {
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ltdc: display-controller@40016800 {
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compatible = "st,stm32-ltdc";
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reg = <0x40016800 0x200>;
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resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
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clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
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pinctrl-0 = <<dc_pins>;
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status = "okay";
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bootph-all;
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};
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};
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};
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&fmc {
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/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
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bank1: bank@0 {
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bootph-all;
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st,sdram-control = /bits/ 8 <NO_COL_8
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NO_ROW_12
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MWIDTH_16
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BANKS_4
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CAS_3
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SDCLK_2
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RD_BURST_EN
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RD_PIPE_DL_0>;
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st,sdram-timing = /bits/ 8 <TMRD_2
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TXSR_6
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TRAS_4
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TRC_6
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TWR_2
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TRP_2
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TRCD_2>;
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/* refcount = (64msec/total_row_sdram)*freq - 20 */
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st,sdram-refcount = < 1542 >;
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};
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};
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&pinctrl {
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ethernet_mii: mii@0 {
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pins {
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pinmux = <STM32_PINMUX('G',13, AF11)>, /* ETH_RMII_TXD0 */
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<STM32_PINMUX('G',14, AF11)>, /* ETH_RMII_TXD1 */
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<STM32_PINMUX('G',11, AF11)>, /* ETH_RMII_TX_EN */
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<STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
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<STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
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<STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
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<STM32_PINMUX('A', 7, AF11)>, /* ETH_RMII_CRS_DV */
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<STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
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<STM32_PINMUX('C', 5, AF11)>; /* ETH_RMII_RXD1 */
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slew-rate = <2>;
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};
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};
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fmc_pins: fmc@0 {
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pins {
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pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
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<STM32_PINMUX('D', 9, AF12)>, /* D14 */
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<STM32_PINMUX('D', 8, AF12)>, /* D13 */
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<STM32_PINMUX('E',15, AF12)>, /* D12 */
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<STM32_PINMUX('E',14, AF12)>, /* D11 */
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<STM32_PINMUX('E',13, AF12)>, /* D10 */
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<STM32_PINMUX('E',12, AF12)>, /* D9 */
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<STM32_PINMUX('E',11, AF12)>, /* D8 */
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<STM32_PINMUX('E',10, AF12)>, /* D7 */
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<STM32_PINMUX('E', 9, AF12)>, /* D6 */
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<STM32_PINMUX('E', 8, AF12)>, /* D5 */
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<STM32_PINMUX('E', 7, AF12)>, /* D4 */
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<STM32_PINMUX('D', 1, AF12)>, /* D3 */
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<STM32_PINMUX('D', 0, AF12)>, /* D2 */
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<STM32_PINMUX('D',15, AF12)>, /* D1 */
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<STM32_PINMUX('D',14, AF12)>, /* D0 */
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<STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
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<STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
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<STM32_PINMUX('G', 5, AF12)>, /* BA1 */
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<STM32_PINMUX('G', 4, AF12)>, /* BA0 */
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<STM32_PINMUX('G', 1, AF12)>, /* A11 */
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<STM32_PINMUX('G', 0, AF12)>, /* A10 */
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<STM32_PINMUX('F',15, AF12)>, /* A9 */
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<STM32_PINMUX('F',14, AF12)>, /* A8 */
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<STM32_PINMUX('F',13, AF12)>, /* A7 */
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<STM32_PINMUX('F',12, AF12)>, /* A6 */
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<STM32_PINMUX('F', 5, AF12)>, /* A5 */
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<STM32_PINMUX('F', 4, AF12)>, /* A4 */
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<STM32_PINMUX('F', 3, AF12)>, /* A3 */
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<STM32_PINMUX('F', 2, AF12)>, /* A2 */
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<STM32_PINMUX('F', 1, AF12)>, /* A1 */
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<STM32_PINMUX('F', 0, AF12)>, /* A0 */
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<STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
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<STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
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<STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
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<STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
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<STM32_PINMUX('C', 3, AF12)>, /* SDCKE0 */
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<STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
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slew-rate = <2>;
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};
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};
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ltdc_pins: ltdc@0 {
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pins {
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pinmux = <STM32_PINMUX('E', 4, AF14)>, /* B0 */
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<STM32_PINMUX('G',12, AF14)>, /* B4 */
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<STM32_PINMUX('I', 9, AF14)>, /* VSYNC */
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<STM32_PINMUX('I',10, AF14)>, /* HSYNC */
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<STM32_PINMUX('I',14, AF14)>, /* CLK */
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<STM32_PINMUX('I',15, AF14)>, /* R0 */
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<STM32_PINMUX('J', 0, AF14)>, /* R1 */
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<STM32_PINMUX('J', 1, AF14)>, /* R2 */
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<STM32_PINMUX('J', 2, AF14)>, /* R3 */
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<STM32_PINMUX('J', 3, AF14)>, /* R4 */
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<STM32_PINMUX('J', 4, AF14)>, /* R5 */
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<STM32_PINMUX('J', 5, AF14)>, /* R6 */
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<STM32_PINMUX('J', 6, AF14)>, /* R7 */
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<STM32_PINMUX('J', 7, AF14)>, /* G0 */
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<STM32_PINMUX('J', 8, AF14)>, /* G1 */
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<STM32_PINMUX('J', 9, AF14)>, /* G2 */
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<STM32_PINMUX('J',10, AF14)>, /* G3 */
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<STM32_PINMUX('J',11, AF14)>, /* G4 */
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<STM32_PINMUX('J',13, AF14)>, /* B1 */
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<STM32_PINMUX('J',14, AF14)>, /* B2 */
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<STM32_PINMUX('J',15, AF14)>, /* B3 */
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<STM32_PINMUX('K', 0, AF14)>, /* G5 */
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<STM32_PINMUX('K', 1, AF14)>, /* G6 */
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<STM32_PINMUX('K', 2, AF14)>, /* G7 */
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<STM32_PINMUX('K', 4, AF14)>, /* B5 */
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<STM32_PINMUX('K', 5, AF14)>, /* B6 */
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<STM32_PINMUX('K', 6, AF14)>, /* B7 */
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<STM32_PINMUX('K', 7, AF14)>; /* DE */
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slew-rate = <2>;
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};
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};
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qspi_pins: qspi@0 {
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pins {
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pinmux = <STM32_PINMUX('B', 2, AF9)>, /* CLK */
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<STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */
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<STM32_PINMUX('D',11, AF9)>, /* BK1_IO0 */
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<STM32_PINMUX('D',12, AF9)>, /* BK1_IO1 */
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<STM32_PINMUX('D',13, AF9)>, /* BK1_IO3 */
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<STM32_PINMUX('E', 2, AF9)>; /* BK1_IO2 */
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slew-rate = <2>;
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};
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};
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usart1_pins_b: usart1-1 {
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bootph-all;
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pins1 {
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bootph-all;
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};
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pins2 {
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bootph-all;
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};
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};
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};
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&pwrcfg {
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bootph-all;
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};
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&qspi {
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reg = <0xa0001000 0x1000>, <0x90000000 0x1000000>;
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qflash0: n25q128a@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <108000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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reg = <0>;
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};
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};
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