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https://github.com/AsahiLinux/u-boot
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390 lines
9.6 KiB
C
390 lines
9.6 KiB
C
/*
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* Copyright 2006 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#ifdef CONFIG_FSL_I2C
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#ifdef CONFIG_HARD_I2C
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#include <command.h>
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#include <i2c.h> /* Functional interface */
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#include <asm/io.h>
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#include <asm/fsl_i2c.h> /* HW definitions */
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#define I2C_TIMEOUT (CFG_HZ / 4)
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#define I2C_READ_BIT 1
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#define I2C_WRITE_BIT 0
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DECLARE_GLOBAL_DATA_PTR;
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/* Initialize the bus pointer to whatever one the SPD EEPROM is on.
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* Default is bus 0. This is necessary because the DDR initialization
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* runs from ROM, and we can't switch buses because we can't modify
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* the global variables.
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*/
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#ifdef CFG_SPD_BUS_NUM
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static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM;
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#else
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static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
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#endif
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static unsigned int i2c_bus_speed[2] = {CFG_I2C_SPEED, CFG_I2C_SPEED};
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static const struct fsl_i2c *i2c_dev[2] = {
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(struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET),
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#ifdef CFG_I2C2_OFFSET
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(struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET)
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#endif
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};
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/* I2C speed map for a DFSR value of 1 */
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/*
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* Map I2C frequency dividers to FDR and DFSR values
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*
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* This structure is used to define the elements of a table that maps I2C
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* frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
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* programmed into the Frequency Divider Ratio (FDR) and Digital Filter
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* Sampling Rate (DFSR) registers.
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*
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* The actual table should be defined in the board file, and it must be called
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* fsl_i2c_speed_map[].
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*
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* The last entry of the table must have a value of {-1, X}, where X is same
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* FDR/DFSR values as the second-to-last entry. This guarantees that any
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* search through the array will always find a match.
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*
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* The values of the divider must be in increasing numerical order, i.e.
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* fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
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*
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* For this table, the values are based on a value of 1 for the DFSR
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* register. See the application note AN2919 "Determining the I2C Frequency
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* Divider Ratio for SCL"
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*/
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static const struct {
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unsigned short divider;
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u8 dfsr;
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u8 fdr;
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} fsl_i2c_speed_map[] = {
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{160, 1, 32}, {192, 1, 33}, {224, 1, 34}, {256, 1, 35},
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{288, 1, 0}, {320, 1, 1}, {352, 6, 1}, {384, 1, 2}, {416, 6, 2},
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{448, 1, 38}, {480, 1, 3}, {512, 1, 39}, {544, 11, 3}, {576, 1, 4},
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{608, 22, 3}, {640, 1, 5}, {672, 32, 3}, {704, 11, 5}, {736, 43, 3},
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{768, 1, 6}, {800, 54, 3}, {832, 11, 6}, {896, 1, 42}, {960, 1, 7},
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{1024, 1, 43}, {1088, 22, 7}, {1152, 1, 8}, {1216, 43, 7}, {1280, 1, 9},
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{1408, 22, 9}, {1536, 1, 10}, {1664, 22, 10}, {1792, 1, 46},
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{1920, 1, 11}, {2048, 1, 47}, {2176, 43, 11}, {2304, 1, 12},
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{2560, 1, 13}, {2816, 43, 13}, {3072, 1, 14}, {3328, 43, 14},
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{3584, 1, 50}, {3840, 1, 15}, {4096, 1, 51}, {4608, 1, 16},
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{5120, 1, 17}, {6144, 1, 18}, {7168, 1, 54}, {7680, 1, 19},
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{8192, 1, 55}, {9216, 1, 20}, {10240, 1, 21}, {12288, 1, 22},
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{14336, 1, 58}, {15360, 1, 23}, {16384, 1, 59}, {18432, 1, 24},
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{20480, 1, 25}, {24576, 1, 26}, {28672, 1, 62}, {30720, 1, 27},
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{32768, 1, 63}, {36864, 1, 28}, {40960, 1, 29}, {49152, 1, 30},
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{61440, 1, 31}, {-1, 1, 31}
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};
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/**
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* Set the I2C bus speed for a given I2C device
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*
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* @param dev: the I2C device
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* @i2c_clk: I2C bus clock frequency
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* @speed: the desired speed of the bus
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*
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* The I2C device must be stopped before calling this function.
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*
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* The return value is the actual bus speed that is set.
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*/
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static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
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unsigned int i2c_clk, unsigned int speed)
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{
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unsigned short divider = min(i2c_clk / speed, (unsigned short) -1);
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unsigned int i;
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/*
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* We want to choose an FDR/DFSR that generates an I2C bus speed that
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* is equal to or lower than the requested speed. That means that we
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* want the first divider that is equal to or greater than the
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* calculated divider.
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*/
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for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
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if (fsl_i2c_speed_map[i].divider >= divider) {
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u8 fdr, dfsr;
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dfsr = fsl_i2c_speed_map[i].dfsr;
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fdr = fsl_i2c_speed_map[i].fdr;
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speed = i2c_clk / fsl_i2c_speed_map[i].divider;
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writeb(fdr, &dev->fdr); /* set bus speed */
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writeb(dfsr, &dev->dfsrr); /* set default filter */
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break;
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}
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return speed;
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}
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void
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i2c_init(int speed, int slaveadd)
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{
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struct fsl_i2c *dev;
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dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET);
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writeb(0, &dev->cr); /* stop I2C controller */
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udelay(5); /* let it shutdown in peace */
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i2c_bus_speed[0] = set_i2c_bus_speed(dev, gd->i2c1_clk, speed);
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writeb(slaveadd << 1, &dev->adr); /* write slave address */
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writeb(0x0, &dev->sr); /* clear status register */
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writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
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#ifdef CFG_I2C2_OFFSET
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dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET);
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writeb(0, &dev->cr); /* stop I2C controller */
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udelay(5); /* let it shutdown in peace */
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i2c_bus_speed[1] = set_i2c_bus_speed(dev, gd->i2c2_clk, speed);
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writeb(slaveadd << 1, &dev->adr); /* write slave address */
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writeb(0x0, &dev->sr); /* clear status register */
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writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
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#endif
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}
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static __inline__ int
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i2c_wait4bus(void)
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{
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ulong timeval = get_timer(0);
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while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
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if (get_timer(timeval) > I2C_TIMEOUT) {
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return -1;
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}
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}
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return 0;
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}
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static __inline__ int
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i2c_wait(int write)
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{
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u32 csr;
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ulong timeval = get_timer(0);
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do {
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csr = readb(&i2c_dev[i2c_bus_num]->sr);
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if (!(csr & I2C_SR_MIF))
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continue;
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writeb(0x0, &i2c_dev[i2c_bus_num]->sr);
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if (csr & I2C_SR_MAL) {
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debug("i2c_wait: MAL\n");
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return -1;
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}
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if (!(csr & I2C_SR_MCF)) {
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debug("i2c_wait: unfinished\n");
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return -1;
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}
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if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
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debug("i2c_wait: No RXACK\n");
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return -1;
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}
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return 0;
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} while (get_timer (timeval) < I2C_TIMEOUT);
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debug("i2c_wait: timed out\n");
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return -1;
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}
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static __inline__ int
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i2c_write_addr (u8 dev, u8 dir, int rsta)
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{
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writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
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| (rsta ? I2C_CR_RSTA : 0),
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&i2c_dev[i2c_bus_num]->cr);
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writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr);
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if (i2c_wait(I2C_WRITE_BIT) < 0)
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return 0;
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return 1;
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}
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static __inline__ int
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__i2c_write(u8 *data, int length)
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{
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int i;
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writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
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&i2c_dev[i2c_bus_num]->cr);
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for (i = 0; i < length; i++) {
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writeb(data[i], &i2c_dev[i2c_bus_num]->dr);
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if (i2c_wait(I2C_WRITE_BIT) < 0)
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break;
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}
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return i;
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}
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static __inline__ int
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__i2c_read(u8 *data, int length)
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{
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int i;
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writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
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&i2c_dev[i2c_bus_num]->cr);
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/* dummy read */
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readb(&i2c_dev[i2c_bus_num]->dr);
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for (i = 0; i < length; i++) {
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if (i2c_wait(I2C_READ_BIT) < 0)
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break;
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/* Generate ack on last next to last byte */
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if (i == length - 2)
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writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
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&i2c_dev[i2c_bus_num]->cr);
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/* Generate stop on last byte */
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if (i == length - 1)
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writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr);
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data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
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}
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return i;
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}
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int
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i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
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{
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int i = -1; /* signal error */
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u8 *a = (u8*)&addr;
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if (i2c_wait4bus() >= 0
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&& i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
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&& __i2c_write(&a[4 - alen], alen) == alen)
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i = 0; /* No error so far */
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if (length
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&& i2c_write_addr(dev, I2C_READ_BIT, 1) != 0)
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i = __i2c_read(data, length);
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writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
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if (i == length)
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return 0;
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return -1;
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}
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int
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i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
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{
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int i = -1; /* signal error */
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u8 *a = (u8*)&addr;
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if (i2c_wait4bus() >= 0
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&& i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
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&& __i2c_write(&a[4 - alen], alen) == alen) {
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i = __i2c_write(data, length);
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}
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writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
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if (i == length)
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return 0;
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return -1;
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}
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int
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i2c_probe(uchar chip)
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{
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/* For unknow reason the controller will ACK when
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* probing for a slave with the same address, so skip
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* it.
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*/
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if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1))
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return -1;
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return i2c_read(chip, 0, 0, NULL, 0);
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}
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uchar
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i2c_reg_read(uchar i2c_addr, uchar reg)
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{
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uchar buf[1];
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i2c_read(i2c_addr, reg, 1, buf, 1);
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return buf[0];
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}
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void
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i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
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{
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i2c_write(i2c_addr, reg, 1, &val, 1);
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}
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int i2c_set_bus_num(unsigned int bus)
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{
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#ifdef CFG_I2C2_OFFSET
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if (bus > 1) {
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#else
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if (bus > 0) {
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#endif
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return -1;
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}
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i2c_bus_num = bus;
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return 0;
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}
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int i2c_set_bus_speed(unsigned int speed)
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{
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unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk;
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writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */
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i2c_bus_speed[i2c_bus_num] =
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set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed);
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writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */
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return 0;
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}
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unsigned int i2c_get_bus_num(void)
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{
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return i2c_bus_num;
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}
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unsigned int i2c_get_bus_speed(void)
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{
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return i2c_bus_speed[i2c_bus_num];
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}
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#endif /* CONFIG_HARD_I2C */
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#endif /* CONFIG_FSL_I2C */
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