mirror of
https://github.com/AsahiLinux/u-boot
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1c2479a5fa
This driver manages the SPI controller present on this SoC. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org>
171 lines
3.2 KiB
Text
171 lines
3.2 KiB
Text
/*
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* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <dt-bindings/clock/bcm3380-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/reset/bcm3380-reset.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "brcm,bcm3380";
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aliases {
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spi0 = &spi;
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};
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cpus {
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reg = <0x14e00000 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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u-boot,dm-pre-reloc;
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cpu@0 {
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compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
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device_type = "cpu";
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reg = <0>;
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u-boot,dm-pre-reloc;
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};
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cpu@1 {
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compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
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device_type = "cpu";
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reg = <1>;
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u-boot,dm-pre-reloc;
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};
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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u-boot,dm-pre-reloc;
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periph_osc: periph-osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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u-boot,dm-pre-reloc;
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};
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periph_clk0: periph-clk@14e00004 {
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compatible = "brcm,bcm6345-clk";
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reg = <0x14e00004 0x4>;
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#clock-cells = <1>;
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};
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periph_clk1: periph-clk@14e00008 {
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compatible = "brcm,bcm6345-clk";
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reg = <0x14e00008 0x4>;
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#clock-cells = <1>;
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};
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};
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ubus {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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u-boot,dm-pre-reloc;
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memory-controller@12000000 {
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compatible = "brcm,bcm6328-mc";
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reg = <0x12000000 0x1000>;
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u-boot,dm-pre-reloc;
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};
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periph_rst0: reset-controller@14e0008c {
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compatible = "brcm,bcm6345-reset";
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reg = <0x14e0008c 0x4>;
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#reset-cells = <1>;
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};
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periph_rst1: reset-controller@14e00090 {
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compatible = "brcm,bcm6345-reset";
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reg = <0x14e00090 0x4>;
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#reset-cells = <1>;
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};
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pll_cntl: syscon@14e00094 {
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compatible = "syscon";
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reg = <0x14e00094 0x4>;
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};
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syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&pll_cntl>;
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offset = <0x0>;
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mask = <0x1>;
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};
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wdt: watchdog@14e000dc {
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compatible = "brcm,bcm6345-wdt";
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reg = <0x14e000dc 0xc>;
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clocks = <&periph_osc>;
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdt>;
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};
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gpio0: gpio-controller@14e00100 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x14e00100 0x4>, <0x14e00108 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio1: gpio-controller@14e00104 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x14e00104 0x4>, <0x14e0010c 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <3>;
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status = "disabled";
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};
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uart0: serial@14e00200 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x14e00200 0x18>;
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clocks = <&periph_osc>;
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status = "disabled";
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};
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uart1: serial@14e00220 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x14e00220 0x18>;
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clocks = <&periph_osc>;
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status = "disabled";
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};
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spi: spi@14e02000 {
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compatible = "brcm,bcm6358-spi";
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reg = <0x14e02000 0x70c>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&periph_clk0 BCM3380_CLK0_SPI>;
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resets = <&periph_rst0 BCM3380_RST0_SPI>;
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spi-max-frequency = <25000000>;
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num-cs = <6>;
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status = "disabled";
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};
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leds: led-controller@14e00f00 {
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compatible = "brcm,bcm6328-leds";
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reg = <0x14e00f00 0x1c>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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};
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