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https://github.com/AsahiLinux/u-boot
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565d77b4c0
The rk3128 DT node names should be generic. Rename them to the pattern defined in the DT bindings. Signed-off-by: Johan Jonker <jbx6244@gmail.com>
99 lines
1.6 KiB
Text
99 lines
1.6 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*/
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/dts-v1/;
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#include "rk3128.dtsi"
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/ {
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model = "Rockchip RK3128 Evaluation board";
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compatible = "rockchip,rk3128-evb", "rockchip,rk3128";
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chosen {
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stdout-path = &uart2;
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};
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memory@60000000 {
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device_type = "memory";
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reg = <0x60000000 0x40000000>;
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};
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vcc5v0_otg: vcc5v0-otg-drv {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_otg";
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gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&otg_vbus_drv>;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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vcc5v0_host: vcc5v0-host-drv {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_host";
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gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&host_vbus_drv>;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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};
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};
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&emmc {
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fifo-mode;
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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hym8563: hym8563@51 {
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compatible = "haoyu,hym8563";
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reg = <0x51>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "xin32k";
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};
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};
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&u2phy {
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status = "okay";
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};
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&u2phy_otg {
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status = "okay";
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};
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&u2phy_host {
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status = "okay";
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};
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&usb_host_ehci {
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status = "okay";
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};
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&usb_host_ohci {
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status = "okay";
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};
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&usb_otg {
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vbus-supply = <&vcc5v0_otg>;
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status = "okay";
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};
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&pinctrl {
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usb_otg {
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otg_vbus_drv: host-vbus-drv {
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rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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usb_host {
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host_vbus_drv: host-vbus-drv {
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rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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