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https://github.com/AsahiLinux/u-boot
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366a863e65
The sar-reg0 alias was left over from an earlier iteration of the
patches adding support for this board. Remove the unused alias.
Fixes: 6cc8b5db40 ("arm: mvebu: Add RD-AC5X board")
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
128 lines
2.6 KiB
Text
128 lines
2.6 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree For RD-AC5X.
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*
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* Copyright (C) 2021 Marvell
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* Copyright (C) 2022 Allied Telesis Labs
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*/
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/*
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* Device Tree file for Marvell Alleycat 5X development board
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* This board file supports the B configuration of the board
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*/
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/dts-v1/;
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#include "ac5-98dx35xx.dtsi"
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/ {
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model = "Marvell RD-AC5X Board";
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compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5";
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aliases {
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serial0 = &uart0;
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spiflash0 = &spiflash0;
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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ethernet0 = ð0;
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ethernet1 = ð1;
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spi0 = &spi0;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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usb0 = &usb0;
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usb1 = &usb1;
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pinctrl0 = &pinctrl0;
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};
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usb1phy: usb-phy {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&uart0 {
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status = "okay";
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};
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&mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&i2c0 {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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};
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ð0 {
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status = "okay";
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phy-handle = <&phy0>;
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};
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/* USB0 is a host USB */
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&usb0 {
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status = "okay";
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};
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/* USB1 is a peripheral USB */
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&usb1 {
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status = "okay";
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phys = <&usb1phy>;
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phy-names = "usb-phy";
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dr_mode = "peripheral";
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};
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&spi0 {
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status = "okay";
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spiflash0: flash@0 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
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spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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&pinctrl0 {
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/*
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* MPP Bus: MPP# mode#
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* eMMC [0-11] 0x1
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* SPI[0] [12-17] 0x1
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* TSEN_INT [18] 0x1
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* DEV_INIT [19] 0x1
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* SPI[1] [20-23] 0x3
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* UART[1] [24-25] 0x3
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* I2C[0] [26-27] 0x1
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* XSMI[0] [28-29] 0x1 // SCH use SMI[0], reversed due to CPSS problem
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* SMI[1] [30-31] 0x2 // SCH use XSMI[1], reversed due to CPSS problem
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* UART[0] [32-33] 0x1
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* OOB_SMI [34-35] 0x1
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* PTP_CLK0_OUT [36] 0x1
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* PTP_PULSE_OUT [37] 0x1
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* RCVR_CLK_OUT [38] 0x1
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* GPIO(in/out) [39] 0x0
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* GPIO(in/out) [40] 0x0
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* PTP_REF_CLK [41] 0x1
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* PTP_CLK0 [42] 0x1
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* LED0_CLK [43] 0x1
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* LED0_STB [44] 0x1
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* LED0_DATA [45] 0x1
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 1 1 1 1 1 1 1 1 1 1
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1 1 1 1 1 1 1 1 1 1
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3 3 3 3 3 3 1 1 1 1
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2 2 1 1 1 1 1 1 1 0
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0 1 1 1 1 1 >;
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};
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