mirror of
https://github.com/AsahiLinux/u-boot
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4c97c4b590
The x240 and SE240 are a series of L2+ switches from Allied Telesis. There are a number of them in the range but as far as U-Boot is concerned all the CPU block components are the same so there's only one board defined. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
212 lines
4.2 KiB
Text
212 lines
4.2 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "ac5-98dx35xx.dtsi"
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/ {
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model = "Allied Telesis x240";
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compatible = "alliedtelesis,x240", "marvell,ac5x", "marvell,ac5";
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aliases {
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serial0 = &uart0;
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spiflash0 = &spiflash0;
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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spi0 = &spi0;
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i2c0 = &i2c0;
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usb0 = &usb0;
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pinctrl0 = &pinctrl0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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boot-board {
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compatible = "atl,boot-board";
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present-gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
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override-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
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};
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gpio-leds {
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compatible = "gpio-leds";
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fault {
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label = "fault:red";
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gpios = <&system_gpio 11 GPIO_ACTIVE_LOW>;
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default-state = "on";
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};
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};
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};
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&nand {
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pinctrl-names = "default";
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pinctrl-0 = <&nand_pins>;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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status = "okay";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@user {
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reg = <0x00000000 0x10000000>;
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label = "user";
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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mux@71 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nxp,pca9546";
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reg = <0x71>;
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i2c-mux-idle-disconnect;
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reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* MPP36 */
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status = "okay";
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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hwmon@2e {
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compatible = "adi,adt7476";
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reg = <0x2e>;
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};
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rtc@68 {
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compatible = "adi,max31331";
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reg = <0x68>;
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};
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system_gpio: gpio@27 {
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compatible = "nxp,pca9555";
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gpio-controller;
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#gpio-cells= <2>;
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reg = <0x27>;
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interrupt-parent = <&gpio0>;
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interrupts = <25 IRQ_TYPE_LEVEL_LOW>; /* MPP25 */
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};
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};
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};
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};
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&spi0 {
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status = "okay";
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spiflash0: flash@0 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
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spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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&gpio0 {
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phy-reset {
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gpio-hog;
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gpios = <19 GPIO_ACTIVE_LOW>;
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output-high;
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line-name = "phy-reset";
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};
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usb-en {
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gpio-hog;
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gpios = <28 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "usb-en";
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};
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led-oe-n {
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gpio-hog;
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gpios = <23 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "led-oe-n";
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};
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};
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&gpio1 {
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nand-protect {
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gpio-hog;
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gpios = <8 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "nand-protect";
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};
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};
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&pinctrl0 {
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/*
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* MPP Bus: MPP#
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* NF_IO [0-7]
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* NF_Wen [8]
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* NF_ALE [9]
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* NF_CLE [10]
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* NF_Cen [11]
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* QSPI_SCK/SPI0_SCK [12]
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* QSPI_CSn/SPI0_CSn [13]
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* QSPI_DIO[0]/SPI0_MOSI [14]
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* QSPI_DIO[1]/SPI0_MISO [15]
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* NF_Ren [16]
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* NF_RBn [17]
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* WD_INTn [18]
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* B_B_OVRIDE_N [19]
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* GREEN_SW_N [20]
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* PHY_INT_N[0] [21]
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* SPI_WPn [22]
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* LED_OE_N [23]
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* USB_PWR_FLT_N [24]
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* SFP_INT_N [25]
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* I2C0_SCL [26]
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* I2C0_SDA [27]
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* USB_EN [28]
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* MONITOR_INT_N [29]
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* XM1_MDC [30]
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* XM1_MDIO [31]
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* UA0_RXD [32]
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* UA0_TXD [33]
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* PHY_RST0n [34]
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* TPM_INT_N [35]
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* I2CMUX_RESET_N [36]
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* SPI_SRAM_SEL_N [37]
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* B_B_PRESENT [38]
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* SPI_FLASH_SEL_N [39]
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* NF_WP_N [40]
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* POE_INT_N [41]
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* PoE_RST_N [42]
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* LED0_CLK [43]
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* LED0_STB [44]
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* LED0_DATA [45]
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
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0xff 0xff 1 1 1 1 0xff 0xff 0 0
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0 0 0 0 0 0 1 1 0 0
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1 1 1 1 0 0 0 0 0 0
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0 0 0 1 1 1 >;
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nand_pins: nand-pins {
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marvell,pins = <0 1 2 3 4 5 6 7 8 9 10 11 16 17>;
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marvell,function = <2>;
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};
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};
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