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u-boot/arch/riscv/cpu/ax25
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Rick Chen dda00ae4ef riscv: ax25: Andes specific cache shall only support in M-mode 
Limit the cache configuration only can be supported in M mode.
It can not be manipulated in S mode.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08 09:45:08 +08:00
..
cache.c riscv: move the AX25-specific implementation of flush_dcache_all 2019-01-15 09:36:31 +08:00
cpu.c riscv: cache: Implement i/dcache [status, enable, disable] 2018-11-26 13:58:01 +08:00
Kconfig riscv: ax25: Andes specific cache shall only support in M-mode 2019-04-08 09:45:08 +08:00
Makefile riscv: cache: Implement i/dcache [status, enable, disable] 2018-11-26 13:58:01 +08:00