mirror of
https://github.com/AsahiLinux/u-boot
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357 lines
10 KiB
C
357 lines
10 KiB
C
/*
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* (C) Copyright 2006-2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/ppc4xx.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <spd_sdram.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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static inline u32 get_async_pci_freq(void)
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{
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if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
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CONFIG_SYS_BCSR5_PCI66EN)
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return 66666666;
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else
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return 33333333;
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}
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int board_early_init_f(void)
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{
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register uint reg;
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/*--------------------------------------------------------------------
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* Setup the external bus controller/chip selects
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*-------------------------------------------------------------------*/
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mtdcr(EBC0_CFGADDR, EBC0_CFG);
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reg = mfdcr(EBC0_CFGDATA);
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mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
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/*--------------------------------------------------------------------
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* Setup the GPIO pins
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*-------------------------------------------------------------------*/
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/*CPLD cs */
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/*setup Address lines for flash size 64Meg. */
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out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
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out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
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out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
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/*setup emac */
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out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
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out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
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out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
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out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
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out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
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/*UART1 */
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out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
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out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
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out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
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/* external interrupts IRQ0...3 */
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out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
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out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
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out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
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#ifdef CONFIG_440EP
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/*setup USB 2.0 */
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out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
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out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
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out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
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out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
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out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
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#endif
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC0ER, 0x00000000); /* disable all */
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mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
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mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
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mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
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mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC1ER, 0x00000000); /* disable all */
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mtdcr(UIC1CR, 0x00000000); /* all non-critical */
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mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
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mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
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mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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/*--------------------------------------------------------------------
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* Setup other serial configuration
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*-------------------------------------------------------------------*/
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mfsdr(SDR0_PCI0, reg);
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mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */
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mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */
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mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */
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/* Check and reconfigure the PCI sync clock if necessary */
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ppc4xx_pci_sync_clock_config(get_async_pci_freq());
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/*clear tmrclk divisor */
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*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00;
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/*enable ethernet */
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*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x08) = 0xf0;
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#ifdef CONFIG_440EP
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/*enable usb 1.1 fs device and remove usb 2.0 reset */
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*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x09) = 0x00;
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#endif
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/*get rid of flash write protect */
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*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x07) = 0x00;
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return 0;
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}
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int misc_init_r (void)
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{
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uint pbcr;
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int size_val = 0;
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/* Re-do sizing to get full correct info */
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mtdcr(EBC0_CFGADDR, PB0CR);
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pbcr = mfdcr(EBC0_CFGDATA);
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switch (gd->bd->bi_flashsize) {
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case 1 << 20:
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size_val = 0;
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break;
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case 2 << 20:
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size_val = 1;
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break;
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case 4 << 20:
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size_val = 2;
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break;
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case 8 << 20:
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size_val = 3;
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break;
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case 16 << 20:
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size_val = 4;
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break;
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case 32 << 20:
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size_val = 5;
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break;
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case 64 << 20:
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size_val = 6;
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break;
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case 128 << 20:
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size_val = 7;
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break;
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}
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pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
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mtdcr(EBC0_CFGADDR, PB0CR);
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mtdcr(EBC0_CFGDATA, pbcr);
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/* adjust flash start and offset */
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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-CONFIG_SYS_MONITOR_LEN,
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0xffffffff,
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&flash_info[0]);
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return 0;
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}
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int checkboard(void)
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{
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char buf[64];
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int i = getenv_f("serial#", buf, sizeof(buf));
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u8 rev;
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u32 clock = get_async_pci_freq();
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#ifdef CONFIG_440EP
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printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
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#else
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printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
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#endif
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rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
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printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
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if (i > 0) {
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puts(", serial# ");
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puts(buf);
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}
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putc('\n');
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/*
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* Reconfiguration of the PCI sync clock is already done,
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* now check again if everything is in range:
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*/
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if (ppc4xx_pci_sync_clock_config(clock)) {
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printf("ERROR: PCI clocking incorrect (async=%d "
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"sync=%ld)!\n", clock, get_PCI_freq());
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}
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return (0);
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}
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/*************************************************************************
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* initdram -- doesn't use serial presence detect.
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*
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* Assumes: 256 MB, ECC, non-registered
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* PLB @ 133 MHz
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*
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************************************************************************/
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#define NUM_TRIES 64
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#define NUM_READS 10
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void sdram_tr1_set(int ram_address, int* tr1_value)
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{
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int i;
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int j, k;
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volatile unsigned int* ram_pointer = (unsigned int*)ram_address;
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int first_good = -1, last_bad = 0x1ff;
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unsigned long test[NUM_TRIES] = {
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0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
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0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
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0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
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0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
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0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
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0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
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0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
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0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
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0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
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0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
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0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
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0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
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0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
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0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
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0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
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/* go through all possible SDRAM0_TR1[RDCT] values */
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for (i=0; i<=0x1ff; i++) {
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/* set the current value for TR1 */
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mtsdram(SDRAM0_TR1, (0x80800800 | i));
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/* write values */
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for (j=0; j<NUM_TRIES; j++) {
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ram_pointer[j] = test[j];
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/* clear any cache at ram location */
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__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
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}
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/* read values back */
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for (j=0; j<NUM_TRIES; j++) {
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for (k=0; k<NUM_READS; k++) {
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/* clear any cache at ram location */
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__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
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if (ram_pointer[j] != test[j])
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break;
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}
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/* read error */
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if (k != NUM_READS) {
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break;
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}
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}
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/* we have a SDRAM0_TR1[RDCT] that is part of the window */
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if (j == NUM_TRIES) {
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if (first_good == -1)
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first_good = i; /* found beginning of window */
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} else { /* bad read */
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/* if we have not had a good read then don't care */
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if(first_good != -1) {
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/* first failure after a good read */
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last_bad = i-1;
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break;
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}
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}
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}
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/* return the current value for TR1 */
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*tr1_value = (first_good + last_bad) / 2;
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}
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phys_size_t initdram(int board)
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{
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register uint reg;
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int tr1_bank1, tr1_bank2;
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/*--------------------------------------------------------------------
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* Setup some default
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*------------------------------------------------------------------*/
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mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
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mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
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mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
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mtsdram(SDRAM0_CLKTR, 0x40000000); /* ?? */
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mtsdram(SDRAM0_WDDCTR, 0x40000000); /* ?? */
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/*clear this first, if the DDR is enabled by a debugger
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then you can not make changes. */
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mtsdram(SDRAM0_CFG0, 0x00000000); /* Disable EEC */
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/*--------------------------------------------------------------------
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* Setup for board-specific specific mem
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*------------------------------------------------------------------*/
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/*
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* Following for CAS Latency = 2.5 @ 133 MHz PLB
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*/
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mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
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mtsdram(SDRAM0_B1CR, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
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mtsdram(SDRAM0_TR0, 0x410a4012); /* ?? */
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mtsdram(SDRAM0_RTR, 0x04080000); /* ?? */
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mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
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mtsdram(SDRAM0_CFG0, 0x30000000); /* Disable EEC */
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udelay(400); /* Delay 200 usecs (min) */
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/*--------------------------------------------------------------------
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* Enable the controller, then wait for DCEN to complete
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*------------------------------------------------------------------*/
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mtsdram(SDRAM0_CFG0, 0x80000000); /* Enable */
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for (;;) {
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mfsdram(SDRAM0_MCSTS, reg);
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if (reg & 0x80000000)
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break;
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}
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sdram_tr1_set(0x00000000, &tr1_bank1);
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sdram_tr1_set(0x08000000, &tr1_bank2);
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mtsdram(SDRAM0_TR1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
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return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024); /* return bytes */
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}
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/*************************************************************************
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* hw_watchdog_reset
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*
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* This routine is called to reset (keep alive) the watchdog timer
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*
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************************************************************************/
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#if defined(CONFIG_HW_WATCHDOG)
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void hw_watchdog_reset(void)
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{
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}
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#endif
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void board_reset(void)
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{
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/* give reset to BCSR */
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*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x06) = 0x09;
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}
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