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ec48b6c991
Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
30 lines
601 B
C
30 lines
601 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 - 2018 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*/
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#include <common.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_CLOCKS
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/**
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* set_cpu_clk_info - Initialize clock framework
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*
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* Return: 0 always.
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*
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* This function is called from common code after relocation and sets up the
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* clock framework. The framework must not be used before this function had been
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* called.
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*/
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int set_cpu_clk_info(void)
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{
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gd->cpu_clk = get_tbclk();
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gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
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gd->bd->bi_dsp_freq = 0;
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return 0;
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}
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#endif
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