mirror of
https://github.com/AsahiLinux/u-boot
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
118 lines
3.1 KiB
INI
118 lines
3.1 KiB
INI
/*
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* Copyright (C) 2009 Pegatron Corporation
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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* Copyright (C) 2009-2012 Genesi USA, Inc.
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*
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* BASED ON: imx51evk
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*
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* (C) Copyright 2009
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* Stefano Babic DENX Software Engineering sbabic@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer doc/README.imximage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM spi
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/*
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* Essential GPIO settings to be done as early as possible
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* PCBIDn pad settings are all the defaults except #2 which needs HVE off
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*/
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DATA 4 0x73fa8134 0x3 # PCBID0 ALT3 GPIO 3_16
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DATA 4 0x73fa8130 0x3 # PCBID1 ALT3 GPIO 3_17
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DATA 4 0x73fa8128 0x3 # PCBID2 ALT3 GPIO 3_11
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DATA 4 0x73fa8504 0xe4 # PCBID2 PAD ~HVE
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DATA 4 0x73fa8198 0x3 # LED0 ALT3 GPIO 3_13
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DATA 4 0x73fa81c4 0x3 # LED1 ALT3 GPIO 3_14
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DATA 4 0x73fa81c8 0x3 # LED2 ALT3 GPIO 3_15
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/* DDR bus IOMUX PAD settings */
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DATA 4 0x73fa850c 0x20c5 # SDODT1
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DATA 4 0x73fa8510 0x20c5 # SDODT0
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DATA 4 0x73fa84ac 0xc5 # SDWE
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DATA 4 0x73fa84b0 0xc5 # SDCKE0
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DATA 4 0x73fa84b4 0xc5 # SDCKE1
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DATA 4 0x73fa84cc 0xc5 # DRAM_CS0
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DATA 4 0x73fa84d0 0xc5 # DRAM_CS1
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DATA 4 0x73fa882c 0x2 # DRAM_B4
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DATA 4 0x73fa88a4 0x2 # DRAM_B0
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DATA 4 0x73fa88ac 0x2 # DRAM_B1
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DATA 4 0x73fa88b8 0x2 # DRAM_B2
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DATA 4 0x73fa84d4 0xc5 # DRAM_DQM0
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DATA 4 0x73fa84d8 0xc5 # DRAM_DQM1
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DATA 4 0x73fa84dc 0xc5 # DRAM_DQM2
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DATA 4 0x73fa84e0 0xc5 # DRAM_DQM3
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/*
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* Setting DDR for micron
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* 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
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* CAS=3 BL=4
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*/
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/* ESDCTL_ESDCTL0 */
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DATA 4 0x83fd9000 0x82a20000
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/* ESDCTL_ESDCTL1 */
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DATA 4 0x83fd9008 0x82a20000
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/* ESDCTL_ESDMISC */
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DATA 4 0x83fd9010 0xcaaaf6d0
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/* ESDCTL_ESDCFG0 */
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DATA 4 0x83fd9004 0x3f3574aa
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/* ESDCTL_ESDCFG1 */
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DATA 4 0x83fd900c 0x3f3574aa
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/* Init DRAM on CS0 */
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/* ESDCTL_ESDSCR */
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DATA 4 0x83fd9014 0x04008008
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DATA 4 0x83fd9014 0x0000801a
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DATA 4 0x83fd9014 0x0000801b
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DATA 4 0x83fd9014 0x00448019
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DATA 4 0x83fd9014 0x07328018
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DATA 4 0x83fd9014 0x04008008
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DATA 4 0x83fd9014 0x00008010
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DATA 4 0x83fd9014 0x00008010
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DATA 4 0x83fd9014 0x06328018
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DATA 4 0x83fd9014 0x03808019
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DATA 4 0x83fd9014 0x00408019
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DATA 4 0x83fd9014 0x00008000
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/* Init DRAM on CS1 */
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DATA 4 0x83fd9014 0x0400800c
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DATA 4 0x83fd9014 0x0000801e
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DATA 4 0x83fd9014 0x0000801f
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DATA 4 0x83fd9014 0x0000801d
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DATA 4 0x83fd9014 0x0732801c
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DATA 4 0x83fd9014 0x0400800c
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DATA 4 0x83fd9014 0x00008014
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DATA 4 0x83fd9014 0x00008014
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DATA 4 0x83fd9014 0x0632801c
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DATA 4 0x83fd9014 0x0380801d
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DATA 4 0x83fd9014 0x0040801d
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DATA 4 0x83fd9014 0x00008004
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/* Write to CTL0 */
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DATA 4 0x83fd9000 0xb2a20000
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/* Write to CTL1 */
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DATA 4 0x83fd9008 0xb2a20000
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/* ESDMISC */
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DATA 4 0x83fd9010 0x000ad6d0
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/* ESDCTL_ESDCDLYGD */
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DATA 4 0x83fd9034 0x90000000
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DATA 4 0x83fd9014 0x00000000
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