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Some Texas Instruments K3 family of SoCs have one of more Digital Signal Processor (DSP) subsystems that are comprised of either a TMS320C66x CorePac and/or a next-generation TMS320C71x CorePac processor subsystem. Add the device tree bindings document for the C66x DSP devices on these SoCs. The added example illustrates the DT nodes for the first C66x DSP device present on the K3 J721E family of SoCs. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
101 lines
3.5 KiB
Text
101 lines
3.5 KiB
Text
TI K3 DSP devices
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=================
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The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems that
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are used to offload some of the processor-intensive tasks or algorithms, for
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achieving various system level goals.
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These processor sub-systems usually contain additional sub-modules like L1
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and/or L2 caches/SRAMs, an Interrupt Controller, an external memory controller,
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a dedicated local power/sleep controller etc. The DSP processor cores in the
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K3 SoCs is usually either a TMS320C66x CorePac processor or a TMS320C71x CorePac
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processor.
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DSP Device Node:
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================
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Each DSP Core sub-system is represented as a single DT node. Each node has a
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number of required or optional properties that enable the OS running on the
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host processor (Arm CorePac) to perform the device management of the remote
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processor and to communicate with the remote processor.
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Required properties:
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--------------------
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The following are the mandatory properties:
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- compatible: Should be one of the following,
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"ti,j721e-c66-dsp" for C66x DSPs on K3 J721E SoCs
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"ti,j721e-c71-dsp" for C71x DSPs on K3 J721E SoCs
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- reg: Should contain an entry for each value in 'reg-names'.
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Each entry should have the memory region's start address
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and the size of the region, the representation matching
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the parent node's '#address-cells' and '#size-cells' values.
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- reg-names: Should contain strings with the following names, each
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representing a specific internal memory region (if
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present), and should be defined in this order,
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"l2sram", "l1pram", "l1dram"
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NOTE: C71x DSPs do not have a "l1pram" memory.
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- ti,sci: Should be a phandle to the TI-SCI System Controller node
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- ti,sci-dev-id: Should contain the TI-SCI device id corresponding to the
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DSP Core. Please refer to the corresponding System
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Controller documentation for valid values for the DSP
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cores.
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- ti,sci-proc-ids: Should contain 2 integer values. The first cell should
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contain the TI-SCI processor id for the DSP core device
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and the second cell should contain the TI-SCI host id to
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which the processor control ownership should be
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transferred to.
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- resets: Should contain the phandle to the reset controller node
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managing the resets for this device, and a reset
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specifier. Please refer to the following reset bindings
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for the reset argument specifier,
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Documentation/devicetree/bindings/reset/ti,sci-reset.txt
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Example:
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---------
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1. J721E SoC
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/* J721E remoteproc alias */
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aliases {
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rproc6 = &c66_0;
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rproc8 = &c71_0;
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};
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cbass_main: interconnect@100000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71_0 */
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<0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
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<0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>; /* C66_1 */
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/* J721E C66_0 DSP node */
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c66_0: dsp@4d80800000 {
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compatible = "ti,j721e-c66-dsp";
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reg = <0x4d 0x80800000 0x00 0x00048000>,
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<0x4d 0x80e00000 0x00 0x00008000>,
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<0x4d 0x80f00000 0x00 0x00008000>;
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reg-names = "l2sram", "l1pram", "l1dram";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <142>;
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ti,sci-proc-ids = <0x03 0xFF>;
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resets = <&k3_reset 142 1>;
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};
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/* J721E C71_0 DSP node */
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c71_0: dsp@64800000 {
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compatible = "ti,j721e-c71-dsp";
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reg = <0x00 0x64800000 0x00 0x00080000>,
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<0x00 0x64e00000 0x00 0x0000c000>;
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reg-names = "l2sram", "l1dram";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <15>;
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ti,sci-proc-ids = <0x30 0xFF>;
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resets = <&k3_reset 15 1>;
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};
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};
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